UM10850
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User manual
Rev. 2.4 — 13 September 2016
287 of 464
NXP Semiconductors
UM10850
Chapter 22: LPC5410x Serial Peripheral Interfaces (SPI0/1)
22.6.3 SPI Status register
The STAT register provides SPI status flags for software to read, and a control bit for
forcing an end of transfer. Flags other than read-only flags may be cleared by writing ones
to corresponding bits of STAT.
STAT contains 2 error flags (in slave mode only): RXOV and TXUR. These are receiver
overrun and transmit underrun, respectively. If either of these errors occur during
operation, the SPI should be disabled, then re-enabled in order to make sure all internal
states are cleared before attempting to resume operation.
In this register, the following notation is used: RO = Read-only, W1 = write 1 to clear.
[1]
RO = Read-only, W1 = write 1 to clear.
Table 324. SPI Status register (STAT, offset 0x08) bit description
Bit
Symbol
Description
Reset
value
Access
0
RXRDY
Receiver Ready flag. When 1, indicates that data is available to be read from the
receiver buffer. Cleared after a read of the RXDAT register.
0
RO
1
TXRDY
Transmitter Ready flag. When 1, this bit indicates that data may be written to the
transmit buffer. Previous data may still be in the process of being transmitted. Cleared
when data is written to TXDAT or TXDATCTL until the data is moved to the transmit
shift register.
1
RO
2
RXOV
Receiver Overrun interrupt flag. This flag applies only to slave mode (Master = 0). This
flag is set when the beginning of a received character is detected while the receiver
buffer is still in use. If this occurs, the receiver buffer contents are preserved, and the
incoming data is lost. Data received by the SPI should be considered undefined if
RxOv is set.
0
W1
3
TXUR
Transmitter Underrun interrupt flag. This flag applies only to slave mode (Master = 0).
In this case, the transmitter must begin sending new data on the next input clock if the
transmitter is idle. If that data is not available in the transmitter holding register at that
point, there is no data to transmit and the TXUR flag is set. Data transmitted by the SPI
should be considered undefined if TXUR is set.
0
W1
4
SSA
Slave Select Assert. This flag is set whenever any slave select transitions from
deasserted to asserted, in both master and slave modes. This allows determining
when the SPI transmit/receive functions become busy, and allows waking up the
device from reduced power modes when a slave mode access begins. This flag is
cleared by software.
0
W1
5
SSD
Slave Select Deassert. This flag is set whenever any asserted slave selects transition
to deasserted, in both master and slave modes. This allows determining when the SPI
transmit/receive functions become idle. This flag is cleared by software.
0
W1
6
STALLED
Stalled status flag. This indicates whether the SPI is currently in a stall condition.
0
RO
7
END
TRANSFER
End Transfer control bit. Software can set this bit to force an end to the current transfer
when the transmitter finishes any activity already in progress, as if the EOT flag had
been set prior to the last transmission. This capability is included to support cases
where it is not known when transmit data is written that it will be the end of a transfer.
The bit is cleared when the transmitter becomes idle as the transfer comes to an end.
Forcing an end of transfer in this manner causes any specified FRAME_DELAY and
TRANSFER_DELAY to be inserted.
0
RO/W1
8
MSTIDLE
Master idle status flag. This bit is 1 whenever the SPI master function is fully idle. This
means that the transmit holding register is empty and the transmitter is not in the
process of sending data.
1
RO
31:9 -
Reserved. Read value is undefined, only zero should be written.
NA
NA