NXP Semiconductors LPC43Sxx, Руководство пользователя

Страница: 629 / 1441

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 629 of 1441
NXP Semiconductors
UM10503
Chapter 24: LPC43xx/LPC43Sxx SPI Flash Interface (SPIFI)
24.6 Register description
The SPIFI register interface supports word accesses.
24.6.1 SPIFI control register
The SPIFI control register controls the overall operation of the SPIFI and should be written
before any commands are initiated.
Table 447. Register overview: SPIFI (base address 0x4000 3000)
Name Access Address
offset
Description Reset value Reference
CTRL R/W 0x000 SPIFI control register 0x400F FFFF Table 448
CMD R/W 0x004 SPIFI command register 0x0000 0000 Table 449
ADDR R/W 0x008 SPIFI address register 0x0000 0000 Table 450
IDATA R/W 0x00C SPIFI intermediate data register 0x0000 0000 Table 451
CLIMIT R/W 0x010 SPIFI cache limit register 0x0800 0000 Table 452
DATA R/W 0x014 SPIFI data register 0x0000 0000 Table 453
MCMD R/W 0x018 SPIFI memory command register 0x0000 0000 Table 454
STAT R/W 0x01C SPIFI status register 0x0200 0000 Table 455
Table 448. SPIFI control register (CTRL, address 0x4000 3000) bit description
Bit Symbol Value Description Reset
value
15:0 TIMEOUT This field contains the number of serial clock periods without the processor
reading data in memory mode, which will cause the SPIFI hardware to
terminate the command by driving the CS pin high and negating the CMD bit
in the Status register. (This allows the flash memory to enter a lower-power
state.)
If the processor reads data from the flash region after a time-out, the
command in the Memory Command Register is issued again.
0xFFFF
19:16 CSHIGH This field controls the minimum CS high time, expressed as a number of serial
clock periods minus one. 1111
20 - Reserved. -
21 D_PRFTCH_DIS This bit allows conditioning of memory mode prefetches based on the AHB
HPROT (instruction/data) access information. A 1 in this register means that
the SPIFI will not attempt a speculative prefetch when it encounters data
accesses. 0
22 INTEN If this bit is 1 when a command ends, the SPIFI will assert its interrupt request
output. See INTRQ in the status register for further details. 0
23 MODE3 SPI Mode 3 select. 0
0 SCK LOW. The SPIFI drives SCK low after the rising edge at which the last bit
of each command is captured, and keeps it low while CS is HIGH.
1 SCK HIGH. the SPIFI keeps SCK high after the rising edge for the last bit of
each command and while CS is HIGH, and drives it low after it drives CS
LOW. (Known serial flash devices can handle either mode, but some devices
may require a particular mode for proper operation.)
Remark: MODE3, RFCLK, and FBCLK should not all be 1, because in this
case there is no final falling edge on SCK on which to sample the last data bit
of the frame.