NXP Semiconductors LPC43Sxx, Руководство пользователя

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UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 531 of 1441
NXP Semiconductors
UM10503
Chapter 21: LPC43xx/LPC43Sxx General Purpose DMA (GPDMA)
Internally the DMA Controller treats all data as a stream of bytes instead of 16-bit or 32-bit
quantities. This means that when performing mixed-endian activity, where the endianness
of the source and destination are different, byte swapping of the data within the 32-bit data
bus is observed.
Note: If byte swapping is not required, then use of different endianness between the
source and destination addresses must be avoided.
Table 353 shows endian behavior for
different source and destination combinations.
Table 353. Endian behavior
Source
endian Destination
endian Source
width Destination
width Source
transfer
no/byte lane Source data Destination
transfer
no/byte lane
Destination data
Little Little 8 8 1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
21
43
65
87
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
21212121
43434343
65656565
87878787
Little Little 8 16 1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
21
43
65
87
1/[15:0]
2/[31:16]
43214321
87658765
Little Little 8 32 1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
21
43
65
87
1/[31:0] 87654321
Little Little 16 8 1/[7:0]
1/[15:8]
2/[23:16]
2/[31:24]
21
43
65
87
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
21212121
43434343
65656565
87878787
Little Little 16 16 1/[7:0]
1/[15:8]
2/[23:16]
2/[31:24]
21
43
65
87
1/[15:0]
2/[31:16]
43214321
87658765
Little Little 16 32 1/[7:0]
1/[15:8]
2/[23:16]
2/[31:24]
21
43
65
87
1/[31:0] 87654321
Little Little 32 8 1/[7:0]
1/[15:8]
1/[23:16]
1/[31:24]
21
43
65
87
1/[7:0]
2/[15:8]
3/[23:16]
4/[31:24]
21212121
43434343
65656565
87878787
Little Little 32 16 1/[7:0]
1/[15:8]
1/[23:16]
1/[31:24]
21
43
65
87
1/[15:0]
2/[31:16]
43214321
87658765