NXP Semiconductors LPC43Sxx, Руководство пользователя

Страница: 161 / 1441

UM10503 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2015. All rights reserved.
User manual Rev. 2.1 — 10 December 2015 161 of 1441
NXP Semiconductors
UM10503
Chapter 12: LPC43xx/LPC43Sxx Power Management Controller (PMC)
12.2.6 Hardware control of Deep-sleep, Power-down, Deep power-down
modes
The hardware sleep event enable register ( Table 117 ) enables the ARM Cortex-M0 cores
or the ARM Cortex-M4 core to trigger a system power-down (deep-sleep, power-down, or
deep power-down). All of the following conditions must be met for the core that triggers
the system power-down before the part to go into system power-down:
•
The core’s enable bit is set in the PD0_SLEEP0_HW_ENA register. By default the M4
core is enabled.
•
The core receives a WFI/WFE instruction.
•
The core’s SLEEPDEEP bit is set to 1.
In a multi-core system, each core can force the part to enter system power-down
independently of the state (active or sleep) of the other cores. To reduce software
overhead, the hardware sleep event register also allows to delay entering deep-sleep,
power-down or deep power-down modes until software triggers a system power-down in
each core individually. See
Table 114 .
12.2.7 Memory retention in Power-down modes
Table 115 shows which parts of the SRAM memory are preserved in Sleep mode and the
various power-down modes.
In addition, all FIFO memory contained in the peripheral blocks (USB0/1, LCD, CAN,
Ethernet, USART0/2/3, UART) is retained in Sleep mode and Deep-sleep mode but not in
Power-down mode and Deep-power-down mode.
Table 114. PD0_SLEEP0_HW_ENA register settings
M4 core
enabled
for
sleep
events M0APP
and
M0SUB
cores
enabled for
sleep
events PD_SLEEP0_HW
_ENA register
value Description
Yes No 0x1 M4 core controls power-down: System (all cores, peripherals, memories) enters
Deep-sleep, Power-down, or Deep power-down when M4 receives WFI/WFE
instruction and M4 SLEEPDEEP bit =1.
The M0 core can be in active mode, sleep mode, or reset.
This is the default setting.
No Yes 0x2 M0 cores control power-down System (all cores, peripherals, memories) enters
Deep-sleep, Power-down, or Deep power-down when both M0 cores receive
WFI/WFE instruction and M0 SLEEPDEEP bit =1. If one M0 core is in reset or
disabled, the remaining active core alone controls power-down,
The M4 core can be in active mode or sleep mode.
Yes Yes 0x3 System enters Deep-sleep, Power-down, or Deep power-down once each core
has received a WFI/WFE instruction and their SLEEPDEEP bits =1.
Only active cores can control power-down. Cores which are disabled or in reset
are ignored.