UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1173 of 1441
42.1 How to read this chapter
The SSP0/1 controllers are available on all LPC43xx/LPC43Sxx parts.
42.2 Basic configuration
The SSP0/1 are configured as follows:
•
See
for clocking and power control.
•
The SSP0/1 are reset by the SSP0/1_RST (reset #50/51).
•
The SSP0/1 interrupts are connected to slots # 22/23 in the NVIC.
•
For connecting the SSP0/1 receive and transmit lines to the GPDMA, use the
DMAMUX register in the CREG block (see
) and enable the GPDMA
channel in the DMA Channel Configuration registers (
42.3 Features
•
Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire
buses.
•
Synchronous Serial Communication.
•
Supports master or slave operation.
•
Eight-frame FIFOs for both transmit and receive.
•
4-bit to 16-bit frame.
42.4 General description
The SSP is a Synchronous Serial Port (SSP) controller capable of operation on a SPI,
4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.
Only a single master and a single slave can communicate on the bus during a given data
transfer. Data transfers are in principle full duplex, with frames of 4 to 16 bits of data
flowing from the master to the slave and from the slave to the master. In practice it is often
the case that only one of these data flows carries meaningful data.
The LPC43xx has two Synchronous Serial Port controllers -- SSP0 and SSP1.
UM10503
Chapter 42: LPC43xx/LPC43Sxx SSP0/1
Rev. 2.1 — 10 December 2015
User manual
Table 972. SSP0/1 clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to SSP0 register interface
BASE_M4_CLK
CLK_M4_SSP0
up to 204 MHz
SSP0 peripheral clock (PCLK)
BASE_SSP0_CLK
CLK_APB0_SSP0
up to 204 MHz
Clock to SSP1 register interface
BASE_M4_CLK
CLK_M4_SSP1
up to 204 MHz
SSP1 peripheral clock (PCLK)
BASE_SSP1_CLK
CLK_APB2_SSP1
up to 204 MHz
