UM10503
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© NXP B.V. 2015. All rights reserved.
User manual
Rev. 2.1 — 10 December 2015
1033 of 1441
33.1 How to read this chapter
The Motor control PWM is available on all LPC43xx/LPC43Sxx parts.
33.2 Basic configuration
The PWM is configured as follows:
•
See
for clocking and power control.
•
The PWM is reset by the MOTOCONPWM_RST (reset #38).
•
The PWM interrupt is connected to slot #16 in the NVIC.
33.3 Introduction
The Motor Control PWM (MCPWM) is optimized for three-phase AC and DC motor control
applications, but can be used in many other applications that need timing, counting,
capture, and comparison.
33.4 Features
The MCPWM contains three independent channels, each including:
•
a 32-bit Timer/Counter (TC)
•
a 32-bit Limit register (LIM)
•
a 32-bit Match register (MAT)
•
a 10-bit dead-time register (DT) and an associated 10-bit dead-time counter
•
a 32-bit capture register (CAP)
•
two modulated outputs (MCOA and MCOB) with opposite polarities
•
a period interrupt, a pulse-width interrupt, and a capture interrupt
Input pins MCI0-2 can trigger TC capture or increment a channel’s TC. A global Abort
input can force all of the channels into “A passive” state and cause an interrupt.
UM10503
Chapter 33: LPC43xx/LPC43Sxx Motor Control PWM
(MOTOCONPWM)
Rev. 2.1 — 10 December 2015
User manual
Table 799. PWM clocking and power control
Base clock
Branch clock
Operating
frequency
Clock to the PWM Motor control block and
PWM Motocon peripheral clock.
BASE_APB1_
CLK
CLK_APB1_
MOTOCON
up to
204 MHz
