NXP Semiconductors Kinetis KE1xZ256, Справочное руководство

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Clock name Description
BUS_CLK Clocks the Peripherals, divided by DIVSLOW bits inside SCG
FLASH_CLK Clocks the flash module, divided by DIVSLOW bits inside
SCG
FLL_CLK Optional divided FLL source for peripherals
SIRC_CLK Optional divided SIRC source for peripherals
FIRC_CLK Optional divided FIRC source for peripherals
SOSC_CLK
1
Optional divided System Oscillator clock for peripherals.
NOTE: SOSC_CLK/ERCLK/OSCERCLK stands for the
same clock source, in some module chapters.
OSC32_CLK RTC oscillator clock for RTC and peripherals
LPO_CLK Always on low power oscillator clock inside PMC
RTC_CLKOUT Clock output from RTC module for both internal and external
CLKOUT Optional output clock source for external devices
BUSOUT Optional output bus clock through pin for external devices or
diagnostics
1. • For WDOG, its SOSC_CLK is with no dividers, and not gated by SCG_SOSCCSR[SOSCERCLKEN].
• For FTM, its SOSC_CLK is with no dividers, but gated by SCG_SOSCCSR[SOSCERCLKEN].
• For other peripherals (LPUART etc.), its SOSC_CLK is divided by DIVx, and not gated by
SCG_SOSCCSR[SOSCERCLKEN].
17.4 Typical Clock Configuration
The clock dividers are programmed via the SCG module’s clock divider registers. The
following requirements must be met when configuring the clocks for this device:
The following are a few of the more common clock configurations for this device:
Clock Normal Run (Using
LPFLL)
Normal Run (Typically
using FIRC)
VLPR
(Using SIRC or SOSC)
CORE_CLK 72 MHz 48 MHz 4 MHz
SYS_CLK 72 MHz 48 MHz 4 MHz
BUS_CLK 24 MHz 24 MHz 1 MHz
FLASH_CLK 24 MHz 24 MHz 1 MHz
17.4.1 Default start-up clock
In default out of reset, the CPU is clocked from internal Fast IRC (IRC48M). The clocks,
e.g. core clock and bus clock, are programmed via the SCG module. For the default reset
value of divider, please refer to SCG chapter for details.
Chapter 17 Clock Distribution
Kinetis KE1xZ256 Sub-Family Reference Manual, Rev. 3, 07/2018
NXP Semiconductors 359