38.1.2 CMP Clocking Information
The CMP clocking input is as below.
Peripheral Clocking - CMP
PCC_CMP
n
[CGC]
PCC module
SCG module
SCG DIVBUS
CMPn module
BUS_CLK
Peripheral Interface Clock
Registers
Main Clock (internal)
38.1.3 Inter-connectivity Information
The CMP inter-connectivity is shown in following diagram.
Chip-specific information for this module
Kinetis KE1xF Sub-Family Reference Manual, Rev. 4, 06/2019
868
NXP Semiconductors
Содержание KE1xF Series
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