NXP Semiconductors freescale semiconductor MC13211, Справочное руководство

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MC1321x Serial Peripheral Interface (SPI)
MC1321x Reference Manual, Rev. 1.6
4-8 Freescale Semiconductor
4.7.1 SPI Clock Formats
To accommodate a wide variety of synchronous serial peripherals from different manufacturers, the SPI
system has a clock polarity (CPOL) bit and a clock phase (CPHA) control bit to select one of four clock
formats for data transfers. CPOL selectively inserts an inverter in series with the clock. CPHA chooses
between two different clock phase relationships between the clock and data.
Figure 4-6 shows the clock format when CPHA = 0. At the top of the figure, the eight bit times are shown
for reference with bit 1 starting as the slave is selected (SS IN goes low), and bit 8 ends at the last SPSCK
edge. The MSB first line shows the order of SPI data bits determined by the setting in LSBFE. Only the
allowed version of SPSCK polarity is shown, set by the value in CPOL. The SAMPLE IN waveform
applies to the MOSI input of a slave or the MISO input of a master. The MOSI
waveform applies to the
MOSI output pin from a master and the MISO waveform applies to the MISO output from a slave. The
SS1 OUT waveform applies to the slave select output from the master (provided MODFEN and
SSOE = 1). The master SS1 output goes to active low at the start of the first bit time of the transfer.
For a common SPI interface SS1 would go back high at the end of the transfer, however, the modem
protocol as described in
Section 4.9, “Modem SPI Singular Transactions” and Section 4.11, “Modem SPI
Recursive Transactions” , requires that the SS1 (CE) stay low for an entire multibyte transaction.
Figure 4-6. MCU SPI Clock Format (CPHA = 0 and CPOL = 0)
When CPHA = 0, the slave begins to drive its MISO output with the first data bit value (MSB or LSB
depending on LSBFE) when SS1 goes to active low. The first SPSCK edge causes both the master and the
slave to sample the data bit values on their MISO and MOSI inputs, respectively. At the second SPSCK
edge, the SPI shifter shifts one bit position which shifts in the bit value that was just sampled and shifts the
second data bit value out the other end of the shifter to the MOSI and MISO outputs of the master and
slave, respectively.
BIT TIME #
(REFERENCE)
MSB FIRST
SPSCK
(CPOL = 0)
SAMPLE IN
(MISO OR MOSI)
MOSI
(MASTER OUT)
MISO
(SLAVE OUT)
SS OUT
(MASTER)
BIT 7 BIT 6 BIT 2 BIT 1 BIT 0
1 2 6 7 8 ...
...
...