Device Overview
MCF51CN128 Reference Manual
,
Rev. 6
1-10
Freescale Semiconductor
1.4.4
MCG Modes of Operation
The MCG operates in one of the modes described in
. This information has been abbreviated for
clarity’s sake. See the MCG block specification for additional details.
Table 1-6. MCG Modes
Mode
Description
FLL Engaged Internal (FEI)
Default. MCGOUT is derived from the FLL clock, which is controlled by the
internal reference clock. The FLL clock frequency locks to a multiple of the
internal reference frequency. MCGLCLK is derived from the FLL, and the
PLL is disabled in a low-power state.
FLL Engaged External (FEE)
MCGOUT is derived from the FLL clock, which is controlled by the external
reference clock. The external reference clock that is enabled can be
produced by an external crystal, ceramic resonator, or another external
clock source connected to the required crystal oscillator (XOSC).
FLL Bypassed Internal (FBI)
MCGOUT is derived from the internal reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while the MCGOUT clock is driven
from the internal reference clock.
FLL Bypassed External (FBE)
MCGOUT is derived from the external reference clock; the FLL is
operational, but its output clock is not used. This mode is useful to allow
the FLL to acquire its target frequency while MCGOUT is driven from the
external reference clock.
PLL Engaged External (PEE)
MCGOUT is derived from the PLL clock, which is controlled by the external
reference clock. The external reference clock that is enabled can be
produced by an external crystal, ceramic resonator, or another external
clock source connected to the required crystal oscillator (XOSC).
PLL Bypassed External (PBE)
MCGOUT is derived from the external reference clock; the PLL is
operational, but its output clock is not used by the CPU. The external
reference clock that is enabled can be produced by an external crystal,
ceramic resonator, or another external clock source connected to the
required crystal oscillator (XOSC). This mode is useful to allow the PLL to
acquire its target frequency while MCGOUT is driven from the external
reference clock. This mode could also be used to source the Ethernet
MAC clock while running the CPU at a lower clock rate.
Bypassed Low Power Internal (BLPI)
MCGOUT is derived from the internal reference clock.
The PLL and FLL are disabled, and MCGLCLK is not available for BDC
communications. If the BDM becomes enabled, the mode switches to one
of the bypassed internal modes.
