Resets, Interrupts, and General System Control
MCF51CN128 Reference Manual, Rev. 6
Freescale Semiconductor
5-11
5.6
Peripheral Clock Gating
The MCF51CN128 series microcontroller includes a clock gating system to manage the bus clock sources
to the individual peripherals. Using this system, you can enable or disable the bus clock to each of the
peripherals at the clock source, eliminating unnecessary clocks to peripherals which are not in use; thereby
reducing the overall run and wait mode currents.
Out of reset, all peripheral clocks are enabled. For lowest possible run or wait currents, you should disable
the clock source to any peripheral not in use. The actual clock is enabled or disabled immediately
following the write to the clock gating control registers (SCGC1-4). Any peripheral with a gated clock can
not be used unless its clock is enabled. Writing to the registers of a peripheral with a disabled clock (other
than FEC and Mini-FlexBus) has no effect. When the FEC and Mini-FlexBus are not available or their
clocks are disabled, any attempt to read or write the FEC and Mini-Bus register bits results in an access
error.
NOTE
User software must disable the peripheral before disabling the clocks to the
peripheral. When clocks are re-enabled to a peripheral, the peripheral
registers need to be re-initialized by user software.
In stop modes, the bus clock is disabled for all gated peripherals, regardless of the settings in the SCGC1,
SCGC2, SCGC3, and SCGC4 registers.
5.7
Reset, Interrupt, and System Control Registers and Control Bits
One 8-bit register in the direct page register space and eight 8-bit registers in the register space are related
to reset and interrupt systems.
Refer to
Section 4.2, “Detailed Register Addresses and Bit Assignments
,” for the absolute address
assignments for all registers. This section refers to registers and control bits only by their names. A
Freescale-provided equate or header file is used to translate these names into the appropriate absolute
addresses.
Some control bits in the SOPT1 and SPMSC2
registers are related to modes of operation. Although brief
descriptions of these bits are provided here, the related functions are discussed in greater detail in
Chapter 3, “Modes of Operation.”
5.7.1
Interrupt Pin Request Status and Control Register (IRQSC)
This direct page register includes status and control bits which configure the IRQ function, report status,
and acknowledge IRQ events.
7
6
5
4
3
2
1
0
R
0
IRQPDD
IRQEDG
IRQPE
IRQF
0
IRQIE
IRQMOD
W
IRQACK
Reset
0
0
0
0
0
0
0
0
Figure 5-1. Interrupt Request Status and Control Register (IRQSC)
