7.4.1 System clock
Camera engine needs short time to store the data when every pixel edge comes. If the clock frequency of engine is higher, the time
cost is shorter. In this solution, the system clock must be set at 150 MHz when engine is running. The code to configure system
clock is shown as below:
BOARD_BootClockPLL150M();
7.4.2 I
2
C interface
The
flexcomm4
is used as I
2
C function for initializing the camera before the video starts.
7.4.3 Pin function
Table 2. Pin function
Pin
Function number
Input/output
Description
P0_0
15
Input
Camera engine function
P0_1
15
Input
Camera engine function
P0_2
15
Input
Camera engine function
P0_3
15
Input
Camera engine function
P0_4
15
Input
Camera engine function
P0_5
15
Input
Camera engine function
P0_6
15
Input
Camera engine function
P0_7
15
Input
Camera engine function
P0_18
15
Output
Camera engine function
p0_13
0
Input
GPIO as VSYNC input
P0_15
0
Input
GPIO as Pixel clock input
P0_16
2
Output
CLKOUT
P1_20
5
Input/output
FC4_I2C_SCL
P1_21
5
Output
FC4_I2C_SDA
P1_2
6
Output
LSPI_HS_SCK
P0_26
9
Output
LSPI_HS_MOSI
P1_3
6
Input
LSPI_HS_MISO
P1_1
5
Output
LSPI_HS_SSEL1
p1_11
0
Output
GPIO
P0_29
1
Input
FC0_USART_RX
P0_30
1
Output
FC0_USART_TX
From
P0_0
to
P0_7
are the low 8 bits, they can be read by engine at one read instruction which only takes one system clock cycle.
P0_18
is set as camera engine function. It is operated by engine directly such as set logic high level, clear zero, toggle and so on.
P0_18
will be toggled by engine after every VSYNC edge.
NXP Semiconductors
Library and API routine
Camera Interface in LPC55(S)xx, Rev. 3, 07 September 2021
Application Note
5 / 9
