NXP Semiconductors
Quick Start ADC1002S020
QS ADC1002S020
QS_ADC1002S020_2
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Quick Start
Rev. 2 — 11 octobre 2010
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4. Appendix A.1: coherency calculation
The coherency relies on the fact that clock and analog input signal are synchronized and
the first and last samples being captured are adjoining samples: it ensures a continuous
digitized time process for the FFT processing.
To achieve this, one has to follow the equation:
where M is an odd integer equal to the number of periods being acquired and N the
number of samples acquired.
With Fin, Fs and N known, M has to be chosen such that it follows the equation above.
To do this iterative calculation, one has to decide whether Fin or Fs is fixed.
To illustrate this process, let’s consider our current example with Fin = 1 MHz, Fs = 20
Msps and N = 8192 samples acquired:
•
if Fin is fixed, this leads to M = 409 periods of input signal to be acquired and a real
sampling frequency to be Fs = 20.0293399 MHz;
•
if Fs is fixed, this leads to M = 409 periods of input signal to be acquired and a real
input frequency to be Fin = 0.998535156 MHz.
Those values needs to be programmed in the signal generator and clock generator
before capture is done, otherwise the FFT calculation will lead to a non-coherent result
as shown below:
Fig 17. “NXP_ADC_Acquisition” window: non-coherent capture example
The numbers given for SNR, SFDR are completely wrong if coherency is not respected.
