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Register map and OTP memory

A3M38SL039 Airfast Power Amplifier Module with Autobias Control, Rev. 0, September 2022

Data Sheet: Technical Data

Table 10. Register map

Address

(in Decimal)

Register

Attribute

Register

Name

Register Definition

Default

Value

bit7

bit6

bit5

bit4 bit3 bit2 bit1 bit0

System_Reg

N/A

Soft

Reset

Refresh

OTP

N/A

Chip Version [3:0] (Read

only)

8'b0000_0001

OTP

COPY

(RW)

A_Sense_DAC

Reserved

Group A Sense DAC

OTP value

OTP

COPY

(RW)

A_VGS1_DAC

Group A V

GS1

DAC

OTP value

OTP

COPY

(RW)

A_VGS2_DAC

Group A V

GS2

DAC

OTP value

OTP

COPY

(RW)

B_Sense_DAC

Reserved

Group B Sense DAC

OTP value

OTP

COPY

(RW)

B_VGS3_DAC

Group B V

GS3

DAC

OTP value

OTP

COPY

(RW)

B_VGS4_DAC

Group B V

GS4

DAC

OTP value

7–14

—

Reserved

—

Temp_ADC

Temperature Sensor [7:0]

—

Reserved

—

Virtual W

only

EM_Passcode

Engineering Mode (EM) passcode 8'hE3

—

Read Only register (RO)

Read Write register (RW)

Read Write register with OTP overwrite at Startup (RW)

Reserved non-accessible register

Write Only register

Содержание A3M38SL039

Страница 1: ...nications to the module can be accomplished via either I2 C or SPI 3600 4000 MHz Typical LTE Performance Pout 8 W Avg VDD 30 Vdc 1 20 MHz LTE Input Signal PAR 8 dB 0 01 Probability on CCDF 1 Carrier C...

Страница 2: ...verview 11 5 3 Tx enable control 12 5 4 Sense_DAC 12 5 5 VGS_DAC 13 5 6 Engineering Mode EM 13 6 Ordering information 13 7 Component layout and parts list 14 7 1 Component layout 14 7 2 Component desi...

Страница 3: ...ation and function A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 3 33 1 Pinout configuration and function 1 1 Pin connections Figure 1...

Страница 4: ...JEDEC compatible 12 SDA SPI I2 C Serial Data Signal 1 8 V JEDEC compatible 13 CS_B Chip Selection Bar for SPI 1 8 V JEDEC compatible 15 Tx_EN PA Enable Signal 1 8 V JEDEC compatible 16 VCC_ 5V 5 V VCC...

Страница 5: ...2017 3A Charge Device Model per JS 002 2014 C3 2 1 4 Moisture sensitivity level Table 5 Moisture sensitivity level Test Methodology Rating Package Peak Temperature Unit Per JESD22 A113 IPC JEDEC J ST...

Страница 6: ...ditive White Gaussian Noise AWGN with 10 dB PAR ISBW of 400 MHz at 30 Vdc 3 dB Input Overdrive from 8 W Avg Modulated Output Power No Device Degradation 2 2 4 Typical performance Table 9 Typical perfo...

Страница 7: ...written using the Engineering Mode EM sequence however the overwritten values do not persist after a power cycle or a reset The OTP memory can be programmed only by NXP during the manufacturing proces...

Страница 8: ...ense_DAC Reserved Group A Sense DAC OTP value 2 OTP COPY RW A_VGS1_DAC Group A VGS1 DAC OTP value 3 OTP COPY RW A_VGS2_DAC Group A VGS2 DAC OTP value 4 OTP COPY RW B_Sense_DAC Reserved Group B Sense D...

Страница 9: ...tten after the reset operation is completed 0 No 4 Not available N A N A N A 0 3 Chip version bits Inserted by NXP to provide revision information Cannot be changed N A No R 1 A_Sense_DAC 6 7 Not avai...

Страница 10: ...inal stage 8 h00 sets gate to equal ceiling voltage 8 hFF reduces gate voltage by a max value 8 h80 7 14 Reserved N A Not available N A N A N A No 15 Temp_ADC 0 7 Temperature sensor 8 bit DAC value 8...

Страница 11: ...s a duplicate of the carrier however the RF transistor peripheries and quiescent operating points will be different as required by the Doherty operation The module contains four RF LDMOS field effect...

Страница 12: ...n an ON state the RF FET gate terminals are internally decoupled with sufficient capacitance providing a low impedance for wide baseband signals The large capacitance also serves as a charge holding c...

Страница 13: ...stors are manufactured on the same die in close proximity they exhibit similar process and temperature dependencies Both the peaking amplifier and the carrier amplifier operate in the same way with re...

Страница 14: ...22 Data Sheet Technical Data 14 33 7 Component layout and parts list 7 1 Component layout Figure 3 A3M38SL039 reference circuit component layout RFOUT RFIN Rev 4 0 C2 C4 C1 NC VDC2 A1 A0 GND GND TX_EN...

Страница 15: ...Murata Q1 Power Amplifier Module A3M38SL039 NXP R1 0 1 8 W Chip Resistor CRCW08050000Z0EA Vishay PCB Rogers RO4350B 0 020 r 3 66 D139037 MTL Note Component numbers C3 C5 C6 C7 C8 C9 C11 C13 and C16 ar...

Страница 16: ...mplies with SPI mode3 as shown in Figure 5 Figure 5 Serial interface timing diagram Table 16 Serial interface timing specification Symbol Parameter Min ns tSC Setup timing requirement of CS_B both ris...

Страница 17: ...ocol standard It supports I2 C fast mode with a bit rate up to 400 Kbit s It also supports I2 C standard mode with bit rate up to 100 Kbit s 9 2 1 I2 C addressing The two external tri state address pi...

Страница 18: ...rfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 18 33 9 2 2 I2 C instruction set I2 C Write instruction Figure 7 I2 C Write instruction I2 C Read inst...

Страница 19: ...ark A STOP condition followed by a START condition resets the follower state machine and the Device ID read cannot be performed Also a STOP condition or a RESTART condition followed by an access to an...

Страница 20: ...ollower Leader to Follower START 1111 1000 XXXXXXX 0 1 RESTART 1111 1001 3 bytes ID NACK STOP 9 3 I2 C electrical specification and timing for I O stages and bus lines Note VIL 0 3 VDD VIH 0 7 VDD Fig...

Страница 21: ...and the Acknowledge 3 A fast mode I2 C bus device can be used in a standard mode I2 C bus system but the requirement tSU DAT 250 ns must then be met This is automatically the case if the device does n...

Страница 22: ...P Pulse width of spikes that must be suppressed by the input filter 0 50 ns tof Output fall time from VIH min to VIL max Pullup res 250 ohm and max allowed load capacitance Cb 250 ns Cb Capacitive loa...

Страница 23: ...to a 1 state at the same time Soft Reset bit will reset Engineering Mode EM The Soft Reset bit is easily accessible therefore be cautious of the accidental reset Tx_EN must not be active during an OT...

Страница 24: ...Design considerations A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 24 33 Figure 12 Parallel connectivity of grouping...

Страница 25: ...Product marking A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 25 33 11 Product marking Figure 13 Product marking...

Страница 26: ...Package information A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 26 33 12 Package information Figure 14 Package information...

Страница 27: ...Package information A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 27 33 Figure 14 Package information...

Страница 28: ...Package information A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 28 33 Figure 14 Package information...

Страница 29: ...Package information A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 29 33 Figure 14 Package information...

Страница 30: ...Package information A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 30 33 Figure 14 Package information...

Страница 31: ...Package information A3M38SL039 Airfast Power Amplifier Module with Autobias Control Rev 0 September 2022 Data Sheet Technical Data 31 33 Figure 14 Package information...

Страница 32: ...4 Failure analysis At this time because of the physical characteristics of the part failure analysis is limited to electrical signature analysis In cases where NXP is contractually obligated to perfor...

Страница 33: ...ed in NXP data sheets and or specifications can and do vary in different applications and actual performance may vary over time All operating parameters including typicals must be validated for each c...

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