MC56F8367EVM User Manual, Rev. 2
2-30
Freescale Semiconductor
Preliminary
2.15.3 External Memory Control Signal Expansion Connector
The external memory control signal connector contains the 56F8367’s external memory control
signal lines. CS2 and CS3 are MPIO signals, which can be configured as GPIO Port D lines (bits
0 and 1). Refer to
for the names of these signals.
Table 2-18. External Memory Control Signal Connector Description
J6
Pin #
Signal
Pin #
Signal
1
RD
2
IRQA
3
WR
4
IRQB
5
PS / CS0
6
DS / CS1
7
PD0 / CS2 / CAN2_TX
8
PD1 / CS3 / CAN2_RX
PD2 / CS4
PD3 / CS5
PD4 / CS6
PD5 / CS7
9
CLKO
10
RESET
11
GND
12
RSTO
2.15.4 Encoder #0 / Quad Timer Channel A Expansion Connector
The Encoder #0 / Quad Timer Channel A port is an MPIO port attached to the Timer A expansion
connector. This port can be configured as a Quadrature Decoder interface port or as a Quad
Timer port. Refer to
for the signals attached to the connector.
Table 2-19. Timer A Signal Connector Description
J15
Pin #
Signal
Pin #
Signal
1
PHASEA0 / TA0
2
PHASEB0 / TA1
3
INDEX0 / TA2
4
HOME0 / TA3
5
GND
6
+3.3V
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