MS51
Dec. 17, 2019
Page
314
of 316
Rev 1.01
M
S51
SE
RIES
TE
CHNICA
L REF
ERE
N
CE MA
NU
A
L
Instruction
OPCODE
Bytes
Clock Cycles
MS51 V.S. Tradition 80C51
Speed Ratio
RETI
32
1
5
4.8
AJMP addr11
01, 21, 41, 61, 81, A1,
C1, E1[3]
2
3
8
LJMP
addr16
02
3
4
6
SJMP rel
80
2
3
8
JMP
@A+DPTR
73
1
3
8
JZ
rel
60
2
3
8
JNZ
rel
70
2
3
8
JC
rel
40
2
3
8
JNC
rel
50
2
3
8
JB
bit, rel
20
3
5
4.8
JNB
bit, rel
30
3
5
4.8
JBC
bit, rel
10
3
5
4.8
CJNE A, direct, rel
B5
3
5
4.8
CJNE A, #data, rel
B4
3
4
6
CJNE Rn, #data, rel
B8~BF
3
4
6
CJNE @Ri, #data, rel
B6, B7
3
6
4
DJNZ
Rn, rel
D8~DF
2
4
6
DJNZ
direct, rel
D5
3
5
4.8
Note
:
1.
The MS51 does not have external memory bus. MOVX instructions are used to access internal XRAM.
2.
The most three significant bits in the 11-bit address [A10:A8] decide the ACALL hex code. The code will be
[A10,A9,A8,1,0,0,0,1].
3.
The most three significant bits in the 11-bit address [A10:A8] decide the AJMP hex code. The code will be
[A10,A9,A8,0,0,0,0,1].
Table 8.2-1 Instruction Set