Nuvoton Mini57 Series, Техническое справочное руководство, Страница: 349 / 475

Mini57
Apr. 06, 2017 Page 349 of 475 Rev.1.00
MINI5
7
S
E
RI
E
S
TECH
NIC
A
L R
E
F
E
RE
N
CE
MA
N
UA
L
RX Data Word 0 RX Data Word N
Data Frame
SPI_SS
(USCIx_CTL0)
SPI_MOSI
(USCIx_DAT0)
SPI_CLK
(USCIx_CLK)
SPI_MISO
(USCIx_DAT1)
TX Data Word 0 TX Data Word N
Note: x = 0, 1
Figure 6.13-5 4-Wire Full-Duplex SPI Communication Signals (Slave Mode)
6.13.5.3 Serial Bus Clock Configuration
The USCI controller needs the peripheral clock to drive the USCI logic unit to perform the data
transfer. The peripheral clock frequency is equal to PCLK frequency.
In master mode, the frequency of the SPI bus clock is determined by protocol-relative clock
generator. In general, the SPI bus clock is denoted as SPI clock. The frequency of SPI clock is
half of f
SAMP_CLK
, which can be selected by SPCLKSEL (USPI_BRGEN[3:2]). Refer to section
6.11.4.4 for details of protocol-relative clock generator.
In slave mode, the SPI bus clock is provided by an off-chip Master device. The peripheral clock
frequency, f
PCLK
, of SPI Slave device must be 5-times faster than the serial bus clock rate of the
SPI Master device connected together (i.e. the clock rate of serial bus clock < 1/5 peripheral clock
in Slave mode).
In SPI protocol, SCLKMODE (USPI_PROTCTL[7:6]) defines not only the idle state of serial bus
clock but also the serial clock edge used for transmit and receive data. Both Master and Slave
devices on the same communication bus should have the same SCLKMODE configuration. The
four kinds of serial bus clock configuration are shown as Table 6.13-2, and timing diagrams are
shown in Figure 6.13-6, Figure 6.13-7, Figure 6.13-8 and Figure 6.13-9.
SCLKMODE [1:0] SPI Clock Idle State Transmit Timing Receive Timing
0x0 Low Falling edge Rising edge
0x1 Low Rising edge Falling edge
0x2 High Rising edge Falling edge
0x3 High Falling edge Rising edge
Table 6.13-2 Serial Bus Clock Configuration