Nuvoton ARM Cortex NuMicro M451 Series, Техническое справочное руководство

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M451
May. 4, 2018 Page 897 of 1006 Rev.2.08
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Message Interface Register Sets
There are two sets of Interface Registers, which are used to control the CPU access to the Message
RAM. The Interface Registers avoid conflict between the CPU accesses to the Message RAM and
CAN message reception and transmission by buffering the data to be transferred. A complete
Message Object or parts of the Message Object may be transferred between the Message RAM and
the IFn Message Buffer registers in one single transfer.
The function of the two interface register sets is identical except for the Basic test mode. They can be
used the way one set of registers is used for data transfer to the Message RAM while the other set of
registers is used for the data transfer from the Message RAM, allowing both processes to be
interrupted by each other. The Table 6-42 provides an overview of the two Interface Register sets.
Each set of Interface Registers consists of Message Buffer Registers controlled by their own
Command Registers. The Command Mask Register specifies the direction of the data transfer and
which parts of a Message Object will be transferred. The Command Request Register is used to select
a Message Object in the Message RAM as target or source for the transfer and to start the action
specified in the Command Mask Register.
Address IF1 Register Set Address IF2 Register Set
0x20 IF1 Command Request 0x80 IF2 Command Request
0x24 IF1 Command Mask 0x84 IF2 Command Mask
0x28 IF1 Mask 1 0x88 IF2 Mask 1
0x2C IF1 Mask 2 0x8C IF2 Mask 2
0x30 IF1 Arbitration 1 0x90 IF2 Arbitration 1
0x34 IF1 Arbitration 2 0x94 IF2 Arbitration 2
0x38 IF1 Message Control 0x98 IF2 Message Control
0x3C IF1 Data A 1 0x9C IF2 Data A 1
0x40 IF1 Data A 2 0xA0 IF2 Data A 2
0x44 IF1 Data B 1 0xA4 IF2 Data B 1
0x48 IF1 Data B 2 0xA8 IF2 Data B 2
Table 6-42 IF1 and IF2 Message Interface Register