Nuvoton ARM Cortex NuMicro M451 Series, Техническое справочное руководство

Страница: 788 / 1006

M451
May. 4, 2018 Page 788 of 1006 Rev.2.08
M4
51
S
E
RI
E
S
T
E
CH
NICA
L RE
F
E
R
E
NC
E
M
A
NU
A
L
The USB interrupt is used to notify users of any USB event on the bus, and user can read EPSTS
(USBD_EPSTS[31:8]) and EPEVT7~0 (USBD_INTSTS[23:16]) to take necessary responses.
Same as USB interrupt, BUS interrupt notifies users of some bus events, like USB reset,
suspend, time-out and resume. A user can read USBD_ATTR to acknowledge bus events.
Power Saving 6.17.5.6
User can write 0 to USBD_ATTR[4] to disable PHY under special circumstances, like suspend, to
conserve power.
Buffer Control 6.17.5.7
There is 512 bytes SRAM in the controller and the 8 endpoints share this buffer. User shall
configure each endpoint’s effective starting address in the buffer segmentation register before the
USB function active. The
“Buffer Control” block is used to control each endpoint’s effective
starting address and its SRAM size is defined in the USBD_MXPLDx register.
Figure 6.17-3 depicts the starting address for each endpoint according the content of
USBD_BUFSEGx and USBD_MXPLDx registers. If the USBD_BUFSEG0 is programmed as
0x08h and USBD_MXPLD0 is set as 0x40h, the SRAM size of endpoint 0 is start from
0x108h and end in 0x148h. (
Note: The USBD SRAM base is
0x100h).
Setup Token Buffer: 8 bytes
EP0 SRAM Buffer: 64 bytes
EP1 SRAM Buffer: 64 bytes
EP2 SRAM Buffer
EP3 SRAM Buffer
USB SRAM Start Address
EP0 SA = U 0x0108h
MXPLD0 = 0x40
USBD_SRAM = U 0x0100h
EP1 SA = U 0x0148h
MXPLD1 = 0x40
EP2 SA = U 0x0188h
EP3 SA = U 0x0200h
512
bytes
BUFSEG0 = 0x008
BUFSEG1 = 0x048
BUFSEG2 = 0x088
BUFSEG3 = 0x100
Figure 6.17-3 Endpoint SRAM Structure