Numark MIXSTREAM PRO, Руководство по обслуживанию

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1
1
2
2
3
3
4
4
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6
D D
C C
B B
A A
2
200 Scenic View Dr.
Cumberland, RI 02864 6 3/17/2021 Sheet: of
AZ05.SchDoc
INM-PCB-NH08-RearPanel.PrjPcb
Originally Drawn By:
Project:
Sheet:
Variant: Default
Last Modified By:
Last Modified:
Copyright 2021, inMusic Brands
All Rights Reserved
Rev J
nRECOVERY
UART2_RX
UART2_TX
I2C3_SDA
I2C3_SCL
B
T
_
H
O
S
T
_
W
A
K
E
B
T
_
W
A
K
E
ETH_PHYINT
ET
H
_
PH
YR
ST
ET
H
_
M
D
IO
ET
H
_
C
L
K1
2
5
ET
H
_
M
D
C
ET
H
_
PM
E
ETH_RXD0
ETH_RXD1
ETH_RXD2
ETH_RXD3
ETH_RXC
E
T
H
_
T
X
C
E
T
H
_
T
X
C
T
L
E
T
H
_
T
X
D
0
E
T
H
_
T
X
D
1
E
T
H
_
T
X
D
2
E
T
H
_
T
X
D
3
T
O
U
C
H
_
R
E
S
E
T
T
O
U
C
H
_
IN
T
I2
C
4
_
S
C
L
I2
C
4
_
S
D
A
MIPI_PWM
M
IP
I_
T
X
_
D
1
P
M
IP
I_
T
X
_
D
1
N
M
IP
I_
T
X
_
D
3
P
M
IP
I_
T
X
_
D
3
N
M
IP
I_
T
X
_
C
L
K
P
M
IP
I_
T
X
_
C
L
K
N
U
S
B
_
H
O
S
T
2
_
D
M
U
S
B
_
H
O
S
T
2
_
D
P
U
S
B
_
O
T
G
_
ID
U
S
B
_
O
T
G
_
D
E
T
U
S
B
_
H
O
S
T
1
_
D
P
U
S
B
_
O
T
G
_
D
M
U
S
B
_
H
O
S
T
1
_
D
M
U
S
B
_
O
T
G
_
D
P
GPIO_3V3_PD_6
GPIO_3V3_PD_7
GPIO_3V3_PD_8
I2C2_SCL
I2C2_SDA
I2S0_SCLK
I2S0_LRCK_RX
I2S0_SDI
I2S0_SDO0
I2S0_SDO1
I2S0_SDO2
I2S0_SDO3
I2S0_LRCK_TX
M
IP
I_
R
E
S
E
T
n
M
IP
I_
P
O
W
E
R
_
E
N
LED_HEARBEAT
B
T
_
R
E
S
E
T
AUDIO_CLK_SEL_1
AUDIO_CLK_SEL_0
AUDIO_MUTE
AUDIO RESET
AUDIO_POWER_EN
VIN_MON
UART0
UART1
UART2
WiFi/BT
Control Surface
Debug Console
I2C0
I2C1
I2C2
I2C3
I2C4 Touch Panel
Battery Pack
RTC (on SoM)
-unused-
Audio Codec(s)
Peripheral Typical Usage
GND
U
A
R
T
1
_
R
X
D
1
U
A
R
T
1
_
T
X
D
2
G
N
D
3
U
A
R
T
1
_
C
T
S
4
U
A
R
T
1
_
R
T
S
5
G
N
D
6
B
T
_
R
S
T
7
B
T
_
H
O
S
T
_
W
A
K
E
8
B
T
_
W
A
K
E
9
G
N
D
1
0
U
A
R
T
0
_
R
X
1
1
U
A
R
T
0
_
T
X
1
2
G
N
D
1
3
U
A
R
T
0
_
C
T
S
1
4
U
A
R
T
0
_
R
T
S
1
5
G
N
D
1
6
S
O
C
_
R
E
S
E
T
1
7
N
.C
.
1
8
G
N
D
1
9
N
.C
.
2
0
N
.C
.
2
1
T
O
U
C
H
_
IN
T
2
2
T
O
U
C
H
_
R
S
T
2
3
G
N
D
2
4
G
P
IO
_
3
V
3
_
D
2
5
G
P
IO
_
3
V
3
_
D
2
6
G
N
D
2
7
I2
C
4
_
S
C
L
2
8
I2
C
4
_
S
D
A
2
9
G
N
D
3
0
M
IP
I_
T
X
_
D
2
P
3
1
M
IP
I_
T
X
_
D
2
N
3
2
G
N
D
3
3
M
IP
I_
T
X
_
D
1
P
3
4
M
IP
I_
T
X
_
D
1
N
3
5
G
N
D
3
6
M
IP
I_
T
X
_
C
L
K
P
3
7
M
IP
I_
T
X
_
C
L
K
N
3
8
G
N
D
3
9
M
IP
I_
T
X
_
D
0
P
4
0
M
IP
I_
T
X
_
D
0
N
4
1
G
N
D
4
2
M
IP
I_
T
X
_
D
3
P
4
3
M
IP
I_
T
X
_
D
3
N
4
4
G
N
D
4
5
GND
46
PWM0
47
PWM1
48
GND
49
N.C.
50
PWR_HOLD/OTEMP
51
GND
52
PWR_EN
53
GND
166
GPIO_3V3_U
165
GPIO_3V3_U
164
GND
163
GPIO_3V3_U
162
GPIO_3V3_U
161
GND
160
GPIO_3V3_U
159
GPIO_3V3_U
158
GND
64
I2C2_SCL
65
I2C2_SDA
66
GND
67
GPIO_3V3_D
68
GPIO_3V3_D
69
GPIO_3V3_D
70
EMMC_PWR_EN
71
GND
72
GPIO6_B3_d(SPDIF_TX)
73
GPIO2_A2
74
GPIO2_A0
75
GPIO2_A1
76
GPIO6_B0_d(I2S0_CLK)
77
GND
78
I2S_LRCK_RX
79
I2S_LRCK_TX
80
GND
81
I2S_SCLK
82
I2S_SDI
83
GND
84
I2S_SDO0
85
I2S_SDO1
86
GND
87
I2S_SDO2
88
I2S_SDO3
89
GND
90
GN
D
93
SD
M
M
C
_
D
0
94
SD
M
M
C
_
D
1
95
GN
D
96
SD
M
M
C
_
D
2
103
SD
M
M
C
_
D
3
102
GN
D
98
SD
M
M
C
_
C
M
D
100
SD
M
M
C
_
C
L
K
97
GN
D
101
SD
M
M
C
_
D
E
T
99
SD
M
M
C
_
P
W
R
91
GN
D
104
SD
M
M
C
_
W
P
92
N
.C
.
105
GN
D
106
PHY_INT
137
PH
Y_R
S
T
125
GN
D
109
PH
Y_T
X
C
LK
134
GN
D
1
12
MAC_RXCLK
138
M
AC
_M
D
IO
122
GN
D
1
15
PH
Y_T
X
EN
126
GN
D
1
18
M
AC
_C
L
K
1
19
MAC_RXDV
146
GN
D
121
M
AC
_
M
D
C
123
MAC_RXD1
143
GN
D
124
MAC_RXD0
144
PH
Y_T
X
D
1
131
GN
D
127
PH
Y_T
X
D
0
132
MAC_RXD3
140
GN
D
135
MAC_RXD2
141
PH
Y_T
X
D
3
128
GN
D
130
PH
Y_T
X
D
2
129
PH
Y_PM
E
B
120
GN
D
133
GND
145
H
OST
1_
D
M
1
1
1
H
OST
1_D
P
1
10
GND
136
OT
G_D
M
1
17
OT
G_D
P
1
16
GND
139
OT
G_D
ET
1
14
OT
G_I
D
1
13
GND
142
H
OST
2_
D
M
108
H
OST
2_D
P
107
GND
148
UART2_RXD
149
UART2_TXD
150
GND
151
I2C3_SDA
152
I2C3_SCL
153
GND
154
ADCIN1
155
ADCIN2
156
N.C.
167
GPIO7_B7_D
168
WIFI_REG_ON
178
WIFI_HOST_WAKE
179
GND
171
WIFI_D1
169
WIFI_D0
170
GND
174
WIFI_D3
175
WIFI_D2
176
GND
177
WIFI_CLK
172
WIFI_CMD
173
GND
180
N.C.
147
nPBIN
63
RTC_CLKOUT
62
VCC+5
61
VCC+5
60
GND
59
GND
58
VCC_IO
57
VCC_PMU
56
GND
55
VCC_RTC
54
GND
157
U10
AZ05 2GB/8GB
ETH_RXCTL
WIFI_D2
WIFI_D3
WIFI_CMD
WIFI_CLK
WIFI_HOST_WAKE
WIFI_REG_ON
WIFI_D0
WIFI_D1
M
IP
I_
T
X
_
D
0
P
M
IP
I_
T
X
_
D
0
N
M
IP
I_
T
X
_
D
2
P
M
IP
I_
T
X
_
D
2
N
U
A
R
T
1
_
R
X
U
A
R
T
1
_
T
X
U
A
R
T
1
_
C
T
S
U
A
R
T
1
_
R
T
S
U
A
R
T
0
_
R
X
U
A
R
T
0
_
T
X
U
A
R
T
0
_
C
T
S
U
A
R
T
0
_
R
T
S
GPIO_3V3_PU_1
GPIO_3V3_PU_2
RTC_CLK
+5V::SOM
+VCC_RTC
+3.3V::PMU
+3.3V::IO
0
.1
u
F
5
0
V
C
7
2
2
2
u
F
6
.3
V
C
7
1
GND
nPBIN
+5V::SOM
+3.3V::IO
+3.3V::PMU
+VCC_RTC To SOM
To SOM
From SOM
From SOM
Rail Direction Direction
RTC power input of module, sourced by our battery
Main power input of module
IO rail from PMIC, used to gate our IO supplies
PMU rail from PMIC, used to latch main FET
D20
1
2
J14
GND
Install jumper and reset
S
D
M
M
C
_
D
0
S
D
M
M
C
_
D
1
S
D
M
M
C
_
C
M
D
S
D
M
M
C
_
C
L
K
S
D
M
M
C
_
D
E
T
S
D
M
M
C
_
P
W
R
S
D
M
M
C
_
W
P
S
D
M
M
C
_
D
2
S
D
M
M
C
_
D
3
0
.0
0
R
1
11
0
.0
0
R
1
1
2
0
.0
0
R
1
1
3
GND
REV-0
REV-1
REV-2
REV-2 REV-1 REV-0 PCB Rev
- - - A
- - X B
- X - C
- X X D
X - - E
X - X F
X X - G
X X X H
X = Stuff Resistor with 0-Ohm
- = Leave Resistor Unstuffed
HARDWARE REVISION INDICATOR
1
2 3 4
HS1
NH08 HeatSink
0.0
R121
0.0
R122
0.0
R123
0.0
R124
GND
to force ROM updater
S
O
C
_
R
E
S
E
T
PWM1
0
.0
0
R
5
4
REV-3
REV-3
-
-
-
-
-
-
-
-
J
K
L
M
N
X - - -
X
X
X
X
X
-
X
- -
X -
- X
P
Q
R
X
X
X
X - -
X - X
-
X
X X
X X