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HRAM USER/TECHNICAL MANUAL
THEORY OF OPERATION 5
Figure 5-1 shows a block diagram of the HRAM board;
The blocks in this diagram are coordinated with the
schematics in Appendix D. Each block corresponds to a
shaded area of the schematics. In addition, the names
used in the blocks are the same as those used in the
schematics.
5.1 OVERVIEW
Data from the processor is written into the memory via
the 8-bit Data Output (DO) bus. Input buffers isolate
all eight signals. The parity generator computes the
parity of each 8-bit byte, and adds a ninth parity
bit. Each of these 9-bit bytes is then stored in one
of the blocks of RAM chips/ The HRAM uses odd parity.
The design of the HRAM is based on the 16K x 1 dynamic
RAM chip known as the 4116. These chips are arranged
in rows to form 16K 9-bit bytes. The HRAM-64 contains
four rows of RAM chips, the HRAM-48 has three rows,
and the HRAM-32 has two rows. Since each byte
includes a ninth bit for parity error checking, the
HRAM-64 contains 36 RAM chips in all; the 48K
version has 27 chips, and the 32K has 18 chips.
As data is read out of the memory, the parity checker
examines the parity of the byte to insure that it is
odd. The data is then transferred into output latches.
These latches hold the data stable while it is sent
back to the processor on the Data Input (DI) bus.