Chapter 4
Connecting the Signals
©
National Instruments Corporation
4-37
Figures 4-30 and 4-31 show the input and output timing requirements for
UPDATE*.
Figure 4-30.
UPDATE* Input Signal Timing
Figure 4-31.
UPDATE* Output Signal Timing
The DACs are updated within 100 ns of the leading edge. Separate the
UPDATE* pulses with enough time so that new data can be written to
the DAC latches.
The NI 6052E UI counter normally generates UPDATE* unless you select
an external source. The UI counter is started by the WFTRIG signal and can
be stopped by the application software or the internal buffer counter (BC).
D/A conversions generated by an internal or external UPDATE* signal do
not occur when gated by the software command register gate.
When using an external UPDATE* signal, supply at least one more external
update pulse than the number of points you want to generate. Otherwise,
the device does not indicate that the waveform generation is complete.
Rising-Edge
Polarity
Falling-Edge
Polarity
t
w
= 10 ns minimum
t
w
t
w
= 300 to 350 ns
t
w
