5.5 Status System
FRA5014
5-31
5.5.3 Standard event status
The structure of the standard event status is illustrated in Figure 5-4. Details of this status
information are shown in Table 5-4. When “1” is set to bits in the standard event status enable register,
the corresponding bits in the standard event status register become valid, and when the value of any
valid bit becomes “1”, “1” is also set to the ESB bit in the status bit register.
Figure 5-4. Structure of Standard Event Status
Table 5-4. Contents of Standard Event Status Register
Bit
Weight
Description
PON
7
128
Power on
“1” is set to this bit when the power is turned on. It is cleared to zero when
the register is read, and it remains “0” until the next power-on.
URQ
6
64
User request
Always 0 (not being used)
CME
5
32
Command error
“1” is set when a program code syntax error occurs.
EXE
4
16
Execution error
“1” is set when a parameter is outside the setting range, or when settings are
contradictory.
DDE
3
8
Device-specific error
“1” is set when a device-specific error occurs (when a device dependent
error is detected).
QYE
2
4
Query error
“1” is set when attempting to read the output buffer that stores response
messages when the buffer is empty, or when the data in the response
message buffer has been lost.
RQC
1
2
Request control
Always 0 (not being used)
OPC
0
1
Operation complete
“1” is set when overlap command processing has been completed.
Power on (PON)
Always 0 (unused URQ)
Command error (CME)
Execution error (EXE)
Device-specific error (DDE)
Query error (QYE)
Always 0 (unused RQC)
Operation complete (OPC)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
OR
ESR (standard event status register)
ESE (standard event status enable register)
Standard event
status summary
Status byte ESB (bit 5)
&: AND
&
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