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58
NDiS 165 User Manual
Appendix A: Watchdog Timer
CR F2h. Watchdog Timer I(WDT1) Control & Status Register
Location: Address F2h
Attribute: Read/Write
Power Well: VCC
Reset by: LRESET# or PWROK
Default: 00h
Size: 8 bits
Bit
Read/Write
Description
7
R / W
Mouse interrupt reset enables watch-dog timer reload
0: Watchdog Timer I is not affected by mouse interrupt.
1: Watchdog Timer I is reset by mouse interrupt.
6
R / W
Keyboard interrupt reset enables watch-dog timer reload
0: Watchdog Timer I is not affected by keyboard interrupt.
1: Watchdog Timer I is reset by keyboard interrupt.
5
Write “1” Only
Trigger Watchdog Timer I event. This bit is self-clearing.
4
R / W
Write “0” Clear
Watchdog Timer I status bit
0: Watchdog Timer I is running.
1: Watchdog Timer I issues time-out event.
3-0
R / W
These bits select the IRQ resource for the Watchdog Timer I
