N27 Hardware User Guide
Chapter 4 Application Interfaces
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Figure 4-11 PCM sync signal timing
PCM_SYNC
t(sync)
t(syncd)
t(synca)
Figure 4-12 PCM data input timing
t(sus
ync)
t(hsync)
t(clk)
t(clkh)
t(clkl)
PCM_CLK
PCM_SYNC
PCM_DIN
MSB
LSB
t(sudin) t(hdin)
Figure 4-13 PCM data output timing
t(clk)
t(clkh)
t(clkl)
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
t(zdout)
t(susync) t(hsync)
t(pdout
)
t(pdout)
Table 4-1 Timing parameters of PCM interface
Timing Parameter
Minimum Value
Typical Value Maximum Value
Unit
t(sync)
PCM_SYNC cycle
/
125
/
μs
t(synca)
PCM_SYNC
valid
time
/
488
/
ns
t(syncd)
PCM_SYNC invalid
time
/
124.5
/
μs
t(clk)
PCM_CLK cycle
/
488
/
ns
t(clkh)
PCM_CLK high time
/
244
/
ns
