N21
Hardware User Guide
Copyright © Neoway Technology Co., Ltd. All rights reserved.
9
Figure 3-2 Recommended schematic design 2
S
G
D
R4
100 k
Ω
C4
10
μ
F
Q2
Q1
TVS2
C3
470
μ
F
C5
0.1
μ
F
C6
100pF
C7
33 pF
R1
2 k
Ω
R2
10 k
Ω
C1
10
μ
F
C2
0.1
μ
F
B
C
E
VIN (3.6V)
VBAT
PWR_EN
Schematic Design Guidelines
Select an enhanced p-MOSFET at Q1, of which the maximum safe operating voltage and drain
current is high and Rds is low.
Select a common NPN bipolar transistor or a digital NPN bipolar transistor at Q2. Reserve
enough tolerances of resistors at R1 and R2 in design, especially for the situation in which
operating voltage of the bipolar transistor might increase in low temperature.
Place TVS2 close to the input interface of the power supply to clamp the surge voltage before it
enters back-end circuits. Therefore, the back-end components and the module are protected.
Place C3 close to the module. A large bypass tantalum capacitor (220 μF or 100 μF) or aluminum
capacitor (470 μF or 1000 μF) is expected at C1 to reduce voltage drops during bursts. Its
maximum safe operating voltage should be higher than 1.5 times the voltage across the power
supply.
Place a low-ESR bypass capacitor close to the module to filter out high-frequency noise from the
power supply.
PCB Layout Guidelines
Place an ESR capacitor at the output of the power supply to absorb surge current. Place a TVS diode
at the input of VBAT to protect back-end components. The layout of components and PCB trace are
critical to the hardware design of a device. Follow rules below in the power supply design:
TVS diodes dissipate the transient pulse power during a surge and can handle a peak pulse
current of dozens or more than 100 A. They have a short response time. Place the TVS as close
to the interface as possible to ensure that the surge voltage can be clamped before the pulse is
coupled to the neighbor traces.
