48
NED
RCDL2K20CL
UME-0115-02
4.3 Digital Processing flow in FPGA
The
digital processing flow in FPGA is shown below.
Figure 4-3-1 FPGA Processing Block Diagram
Note: When Test Pattern is selected, Black/White reference, Digital Gain & Offset are
omitted.
4.4 Startup
After powering on, the camera will run a startup procedure before it starts getting
images and outputting data. It takes about 10 seconds.
The startup procedure is as follows.
(1)The camera hardware initializes.
(2) Reads out the latest camera settings from the flash memory. (User settings if
any or factory default settings)
(3) Set up the camera with the setting value from the flash memory.
After this sequence, the camera is ready to get images and output data.
Video(8,10bit)
To Channel Link
Driver
Video (8bit)
