Operating Precautions for V
R
4133
TM
No. 11
Usage PCI and Ether/CEU/BCU/CSI (using DMA mode) simultaneously
(Direction of usage)
Details
Using PCI and Ether / CEU / BCU / CSI (using DMA mode) simultaneously may occur a hang-
up, if following 3 conditions are all satisfied:
(1)
CPU reads PCI bus or PCIU register (0x0f000cxx / 0x0f000dxx).
(2)
External PCI master reads or writes SDRAM connected to VR4133.
(3)
When using DMA between Ether/CEU/external I/O(ROM)/CSI and SDRAM.
To avoid this situation, the following workaround must be implemented:
Set 1 to CONFIG_DONE bit of PCIENREG (0x0f000c34) before and after PCI read from.
Example:
LW t0,0xAF00
SW zero,0x0C34(t0) /* CONFIG_DONE <-0 */
LW zero,0x0000(t0) /* read back CONFIG_DONE bit */
LW rx,0(ry) /* PCI bus or PCIU read from CPU */
LI t1,4
SW t1,0x0C34(t0) /* CONFIG_DONE <- 1 */
No. 12
Bus arbitration of Internal Bus Arbiter
(Direction of usage)
Details
If an internal bus request occurs from Ethernet controller and another bus master such as PCI /
BCU / CSI(using DMA) / CEU / CPU / or another Ethernet controller, the internal bus arbiter may
ignore bus arbitration setting of SCUARBITSELREG and gives bus priority to Ethernet controller
continuously.
To prevent this situation use following setting:
DRBS0 of RCV_CFGR0/1(0x0f001618/0x0f001918) = 1 and
DRBS1 of RCV_CFGR0/1(0x0f001618/0x0f001918) = 0.
This setting selects a 2 words burst size. In this case the internal bus arbiter can arbitrate to other
bus master as well.
No. 13
XX-Bit of CP0 status register
(Direction of usage)
Details
The XX-Bit (bit 31) of the CP0 status register does only affect LLD and SCD instructions in 32-bit
supervisor mode and 32-bit user mode. These instructions cause in user or supervisor mode a
reserved instruction exception, if XX-Bit=0. LL instruction, SC instruction LLD instruction (64-bit
mode only) and SCD instruction (64-bit mode only) do not cause a reserved instruction exception
in any case.
This description will be added within the documentation of the VR4133.
No. 14
PCI DMA function
(Specification change notice)
Details
The V
R
4133 PCIU's DMA function (V
R
4133 operates as PCI master and performs DMA transfer
between memory and external PCI device) can not longer be used.
Customer Notification
9
