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User’s Manual U15447EJ1V0UM

CHAPTER 4 CAUTIONS

4.1

DD0

and PORTV

of Target System

(1) V

DD0

in the target system is used to sense the level for target system power supply ON/OFF.

•

When

DD0

is lower than 1 V, it is judged that the target system is not connected, and mapping of the target

memory cannot be performed with a debugger (FCAN cannot be used).

•

When V

DD0

is 1 V or higher, it is judged that the target system is connected, and mapping of the target

memory can be performed with a debugger (FCAN can be used).

(2) PORTV

in the target system is not supplied directly to the emulator chip; it is connected to the target voltage

emulation circuit.

•

When

PORTV

is lower than 3 V, V

(5 V) in the internal emulator is supplied to the emulator chip.

•

When PORTV

is 3 V or higher, a voltage of the same potential as PORTV

in the target system is

generated and supplied to the emulator chip.

Figure 4-1. Schematic Diagram of Power Supply Acquisition

Relay

V850/SF1

I/O chip

Target voltage

emulation

ON/OFF?

Evaluation

chip

Target

system

(5 V)

PORTV

(66 pins)

(8 pins)

IE-703079-MC-EM1

IE-703002-MC

Содержание V850/SF1

Страница 1: ...User s Manual Target device V850 SF1 IE 703079 MC EM1 In circuit Emulator Option Board 1991 Document No U15447EJ1V0UM00 1st edition Date Published September 2001 N CP K Printed in Japan 2001 ...

Страница 2: ...User s Manual U15447EJ1V0UM 2 MEMO ...

Страница 3: ...enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage to property or injury including death to persons arising from defects in NEC semiconductor products customers must incorporate sufficient safety measures in their design such as redundancy fire con...

Страница 4: ...C Electronics Germany GmbH Duesseldorf Germany Tel 0211 65 03 02 Fax 0211 65 03 490 NEC Electronics UK Ltd Milton Keynes UK Tel 01908 691 133 Fax 01908 670 290 NEC Electronics Italiana s r l Milano Italy Tel 02 66 75 41 Fax 02 66 75 42 99 NEC Electronics Germany GmbH Benelux Office Eindhoven The Netherlands Tel 040 2445845 Fax 040 2444580 NEC Electronics France S A Velizy Villacoublay France Tel 0...

Страница 5: ...r the names and functions of parts and the connection of elements refer to the IE 703002 MC User s Manual U11595E To learn about the basic specifications and operation methods Read this manual in the order of the CONTENTS To learn the operation methods and command functions etc of the IE 703002 MC and IE 703079 MC EM1 Read the user s manual of the debugger sold separately that is used Conventions ...

Страница 6: ... U15025E Project Manager U15026E CA850 C Compiler package Ver 2 40 or later Assembly Language U15027E ID850 Integrated debugger Ver 2 40 WindowsTM based Operation To be prepared SM850 System simulator Ver 2 40 Windows based Operation To be prepared SM850 System simulator Ver 2 00 or later External Part User Open Interface Specifications U14873E Basics U13430E Installation U13410E RX850 Real time O...

Страница 7: ...COMPONENTS 18 2 1 Component Names and Functions of IE 703079 MC EM1 18 2 2 Clock Settings 20 2 2 1 Main system clock setting 20 2 2 2 Subsystem clock setting 21 2 3 Illegal Access Detection ROM Setting 22 2 4 CPU Operation Voltage Range Switching Setting 22 CHAPTER 3 FACTORY SETTINGS 23 CHAPTER 4 CAUTIONS 24 4 1 VDD0 and PORTVDD of Target System 24 4 2 NMI Signal 25 4 3 VPP Signal 25 4 4 NMI Signa...

Страница 8: ...em Configuration 12 1 2 Contents in Carton 13 1 3 Accessories 14 1 4 Connection Between IE 703002 MC and IE 703079 MC EM1 16 2 1 IE 703079 MC EM1 18 4 1 Schematic Diagram of Power Supply Acquisition 24 4 2 NMI Signal Flow Path 25 5 1 Equivalent Circuit of Emulation Circuit 29 ...

Страница 9: ...1V0UM 9 LIST OF TABLES Table No Title Page 2 1 Main System Clock Setting 20 2 2 Subsystem Clock Setting 21 2 3 JP1 Setting in IE 703002 MC 22 2 4 JP3 and JP4 Setting in IE 703002 MC 22 4 1 Bus Interface Pin Operation List 26 ...

Страница 10: ...ation controls the IE 703002 MC via Ethernet Power adapter IE 70000 MC PS B AC adapter for in circuit emulator made by NEC Corporation Optional hardware CHAPTER 1 OVERVIEW The IE 703079 MC EM1 is an option board for the IE 703002 MC in circuit emulator By connecting the IE 703079 MC EM1 and IE 703002 MC hardware and software can be debugged efficiently in system development using the V850 SF1 In t...

Страница 11: ...at 5 0 V supply voltage 2 5 W at 16 MHz operation frequency Note Height 50 mm Length 130 mm External dimensions Refer to APPENDIX PACKAGE DRAWINGS Width 252 mm Weight 300 g Note 12 5 W when IE 703002 MC connected to IE 703079 MC EM1 1 3 Function Specifications When Connected to IE 703002 MC Parameter Specification Internal ROM 256 KB In ROMless mode 2 MB Emulation memory capacity External memory W...

Страница 12: ...t emulator IE 703002 MC sold separately 6 In circuit emulator option board IE 703079 MC EM1 this product 7 External logic probe included with IE 703002 MC 8 Socket for target connection YQSOCKET100SDN sold separately 9 Extension probe for GC package SWEX 100SD for GF package SWEX 100SD GF N17DT 10 Connector for emulator connection YQPACK100SD included 11 Connector for target connection NQPACK100SD...

Страница 13: ...sory bag Make sure that the accessory bag contains this manual and the connector accessories If there are missing or damaged items please contact an NEC sales representative or an NEC distributor Figure 1 2 Contents in Carton 1 IE 703079 MC EM1 1 2 Accessory bag 1 3 Guarantee card 1 4 Packing list 1 1 IE 703079 MC EM1 2 Accessory bag 3 Guarantee card 4 Packing list ...

Страница 14: ... U15447EJ1V0UM 14 Check that the accessory bag contains this manual an accessory list 1 and the following accessories a Spacers 4 b Screws washers 4 sets including screws and washer 4 Figure 1 3 Accessories a Spacers b Screws washers ...

Страница 15: ...shown in Figure 1 4 b 3 Connect the IE 703079 MC EM1 to the PGA socket at the back of the IE 703002 MC pod refer to Figure 1 4 c When connecting position the IE 703002 MC and IE 703079 MC EM1 so that they are horizontal 4 Set the PGA socket lever of the IE 703079 MC EM1 to the CLOSE position as shown in Figure 1 4 b 5 Set the IE 703002 MC pod jumpers JP1 to JP3 The factory settings of JP2 are pins...

Страница 16: ...Manual U15447EJ1V0UM 16 Figure 1 4 Connection Between IE 703002 MC and IE 703079 MC EM1 1 2 a Overview b PGA socket lever of IE 703079 MC EM1 CLOSE OPEN IE 703002 MC Nylon rivets Upper cover Screw Washer IE 703079 MC EM1 Spacer ...

Страница 17: ...ER 1 OVERVIEW User s Manual U15447EJ1V0UM 17 Figure 1 4 Connection Between IE 703002 MC and IE 703079 MC EM1 2 2 c Connecting part IE 703079 MC EM1 Pin A1 position Insertion guide IE 703002 MC insertion area ...

Страница 18: ...ositions etc refer to the IE 703002 MC User s Manual U11595E 2 1 Component Names and Functions of IE 703079 MC EM1 Figure 2 1 IE 703079 MC EM1 a Top view b Bottom view V850 SF1 I O chip Direction of pin 1 of connector for target connection FPGA Direction of pin 1 of connector for target connection Connector for target connection JP2 JP3 JP1 CP15 CP1 Connector for IE 703002 MC connection Memory V85...

Страница 19: ...e main system clock 3 JP2 This is the switch jumper for the main system clock supply source Use and retain the factory settings pins 1 and 2 shorted 4 JP3 This is a pin board for supplying the subsystem clock for details refer to 2 2 Clock Settings 5 Connector for IE 703002 MC connection This is a connector for connecting with the IE 703002 MC 6 Connector for target connection This is a connector ...

Страница 20: ...11595E 2 2 1 Main system clock setting Table 2 1 Main System Clock Setting IE 703079 MC EM1 Setting IE 703002 MC Setting Emulator Use Environment Clock Supply Method JP1 JP2 SW1 SW2 JP2 When using emulator as standalone unit Internal clock OFF 1 7 8 2 When using emulator with target system Internal clock ON Caution Emulation cannot be performed by inputting a clock from the target board The specif...

Страница 21: ...when shipped Note 2 When using emulator with target system Internal clockNote 1 Oscillator mounted a 32 768 kHz oscillator is mounted when shipped Note 2 Notes 1 The internal clock does not support the clock input by an oscillator 2 To use a subsystem clock frequency other than 32 768 kHz remove the resonator on JP3 and mount any oscillator The specifications of JP3 are as follows Caution Emulatio...

Страница 22: ...for V850 SF1 is used Note When JP1 is set open keep the removed jumper contact attached to one pin as shown in the drawing on the right JP1 Jumper contact 2 4 CPU Operation Voltage Range Switching Setting If using the IE 703002 MC for an in circuit emulator for the V850 SF1 by connecting the IE 703079 MC EM1 set JP3 and JP4 of the IE 703002 MC as follows Table 2 4 JP3 and JP4 Setting in IE 703002 ...

Страница 23: ...m Description Remark JP1 Oscillator mounted 16 MHz clock supplied for main system clock JP2Note 1 2 Shorted 1 2 3 Internal clock used for main system clock JP3 Oscillator mounted 32 768 kHz clock supplied for subsystem clock Note Use JP2 with the factory settings ...

Страница 24: ...he target memory can be performed with a debugger FCAN can be used 2 PORTVDD in the target system is not supplied directly to the emulator chip it is connected to the target voltage emulation circuit When PORTVDD is lower than 3 V VCC 5 V in the internal emulator is supplied to the emulator chip When PORTVDD is 3 V or higher a voltage of the same potential as PORTVDD in the target system is genera...

Страница 25: ...the emulator chip In addition the DC characteristics change The input voltage becomes VIH 2 0 V MIN VIL 0 8 V MAX and the input current becomes IIN 0 5 µA MAX Figure 4 2 NMI Signal Flow Path 4 3 VPP Signal The VPP signal from the target system is left open in the emulator 4 4 NMI Signal Mask Function When using the P00 NMI pin in the port mode do not mask the NMI signal NMI pin QS3125 IE 703079 MC...

Страница 26: ...A21 Hold the last accessed address Active Active AD0 to AD15 Hi Z Active Active ASTB H Active Active R W H Active Active DSTB H H Active LBEN H Active Active UBEN H Active Active WAIT Invalid Maskable Maskable HLDRQ Maskable Maskable Maskable HLDAK H or L H or L H or L WRL H H H Note WRH H H H Note RD H H Note H Note Active Caution When accessing an FCAN register with the external memory expanded ...

Страница 27: ...e ASTB H Active Active R W H Active Active DSTB H H Active LBEN H Active Active UBEN H Active Active WAIT Invalid Maskable Maskable HLDRQ Maskable Maskable Maskable HLDAK H or L H or L H or L WRL H H H Note WRH H H H Note RD H H Note H Note Active Caution When accessing an FCAN register with the external memory expanded a bus cycle for FCAN access is generated in AD0 to AD15 and A16 to A21 However...

Страница 28: ...arget device is operating on the target system Small differences occur however because the IE system is emulating actual operation 1 Signals input output to from the emulation CPU µPD70F3079Y 2 Other signals The IE 703079 MC EM1 circuit regarding the 1 and 2 signals described above is as follows 1 Signals input output to from the emulation CPU µPD70F3079Y P00 P07 INTP6 to P01 INTP0 P15 SCK1 ASCK0 ...

Страница 29: ...3 P05 INTP4 ADTRG P06 INTP5 P07 INTP6 IN OUT IN OUT P10 SI0 SDA0 P11 SO0 P12 SCK0 SCL0 P13 SI1 RXD0 P14 SO1 TXD0 P15 SCK1 ASCK0 IN OUT P20 SI3 RXD1 P21 SO3 TXD1 P22 SCK3 ASCK1 P23 SI4 P24 SO4 P25 SCK4 P26 P27 P00 NMI P40 AD0 P41 AD1 P42 AD2 P43 AD3 P44 AD4 P45 AD5 P46 AD6 P47 AD7 PD70F3079Y QS3384 OUT IN P30 TI2 TO2 P31 TI3 TO3 P32 TI4 TO4 P33 TI5 TO5 P34 VM45 TI71 IN OUT PD703091R FPGA OR2T40A IN...

Страница 30: ...R2T40A IN OUT QS3384 Connector P60 AD16 P61 AD17 P62 AD18 P63 AD19 P64 AD20 P65 AD21 QS3384 OUT IN PD703091R FPGA OR2T40A OUT QS3384 Connector 74VHC125 74VHC125 PD70F3079Y P70 ANI0 P71 ANI1 P72 ANI2 P73 ANI3 P74 ANI4 P75 ANI5 P76 ANI6 P77 ANI7 IN IN P80 ANI8 P81 ANI9 P82 ANI10 P83 ANI11 AD15 to AD8 P57 to P50 A21 to A16 P65 to P60 QS3384 OUT IN PD703091R FPGA OR2T40A OUT QS3384 Connector 74VHC125 ...

Страница 31: ...UT P100 KR0 TO7 P101 KR1 TI70 P102 KR2 TI00 P103 KR3 TI01 P104 KR4 TO0 P105 KR5 TI10 P106 KR6 TI11 P107 KR7 TO1 QS3384 OUT IN PD703091R FPGA OR2T40A IN QS3384 Connector 74VHC125 P96 HLDRQ IN OUT FPGA OR2T40A 74VHC125 QS3384 P110 WAIT P111 P112 P113 IN OUT PD70F3079F FPGA OR2T40A OUT QS3384 74VHC125 P114 CANTX1 P116 CANTX2 QS3384 IN IN PD70F3079Y FPGA OR2T40A OUT 74VHC125 P115 CANRX1 P117 CANRX2 QS...

Страница 32: ...1 Equivalent Circuit of Emulation Circuit 4 5 VCC 5 1 kΩ 3 V Probe side IE system side Socket RESET X2 PD70F3079Y X1 X1 1 MΩ 1 7 JP1 1 2 3 1 2 shorted JP2 XT2 PD70F3079Y XT1 XT1 1 7 JP3 PD703091R Socket CLKOUT PD703091R PORTVDD 100 F 100 Ω Internal circuit 1 MΩ VCC PC393 Relay 2 2 kΩ 3 3 kΩ VCC G6H 2F µ µ µ µ µ µ ...

Страница 33: ...ARGET INTERFACE CIRCUIT User s Manual U15447EJ1V0UM 33 Figure 5 1 Equivalent Circuit of Emulation Circuit 5 5 Probe side IE system side PD70F3079Y ADCVDD ADCGND CPUREG Open VPP MODE Open X2 Open XT2 Open GND0 GND1 GND2 PORTGND 0 1 F 3 3 V JP1 JP3 µ µ ...

Страница 34: ...al U15447EJ1V0UM 34 APPENDIX PACKAGE DRAWINGS IE 703002 MC IE 703079 MC EM1 Unit mm 571 103 166 58 8 52 90 27 302 Top view Side view IE 703079 MC EM1 IE 703002 MC Bottom view Top view 33 0 130 33 0 Pin 1 direction ...

Страница 35: ...886 2 2719 5951 Address North America NEC Electronics Inc Corporate Communications Dept Fax 1 800 729 9288 1 408 588 6130 Europe NEC Electronics Europe GmbH Technical Documentation Dept Fax 49 211 6503 274 South America NEC do Brasil S A Fax 55 11 6462 6829 Asian Nations except Philippines NEC Electronics Singapore Pte Ltd Fax 65 250 3583 Japan NEC Semiconductor Technical Hotline Fax 81 44 435 960...

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