CHAPTER 14 INSTRUCTION SET
User's Manual U11919EJ3V0UM00
189
Flag
Mnemonic
Operands
Byte
Clock
Operation
Z
AC CY
A,#byte
2
4
A,CY
←
A
−
byte
−
CY
×
×
×
saddr,#byte
3
6
(saddr),CY
←
(saddr)
−
byte
−
CY
×
×
×
A,r
2
4
A,CY
←
A
−
r
−
CY
×
×
×
A,saddr
2
4
A,CY
←
A
−
(saddr)
−
CY
×
×
×
A,!addr16
3
8
A,CY
←
A
−
(addr16)
−
CY
×
×
×
A,[HL]
1
6
A,CY
←
A
−
(HL)
−
CY
×
×
×
SUBC
A,[HL+byte]
2
6
A,CY
←
A
−
(HL+byte)
−
CY
×
×
×
A,#byte
2
4
A
←
A
∧
byte
×
saddr,#byte
3
6
(saddr)
←
(saddr)
∧
byte
×
A,r
2
4
A
←
A
∧
r
×
A,saddr
2
4
A
←
A
∧
(saddr)
×
A,!addr16
3
8
A
←
A
∧
(addr16)
×
A,[HL]
1
6
A
←
A
∧
(HL)
×
AND
A,[HL+byte]
2
6
A
←
A
∧
(HL+byte)
×
A,#byte
2
4
A
←
A
∨
byte
×
saddr,#byte
3
6
(saddr)
←
(saddr)
∨
byte
×
A,r
2
4
A
←
A
∨
r
×
A,saddr
2
4
A
←
A
∨
(saddr)
×
A,!addr16
3
8
A
←
A
∨
(addr16)
×
A,[HL]
1
6
A
←
A
∨
(HL)
×
OR
A,[HL+byte]
2
6
A
←
A
∨
(HL+byte)
×
A,#byte
2
4
A
←
A
∨
byte
×
saddr,#byte
3
6
(saddr)
←
(saddr)
∨
byte
×
A,r
2
4
A
←
A
∨
r
×
A,saddr
2
4
A
←
A
∨
(saddr)
×
A,!addr16
3
8
A
←
A
∨
(addr16)
×
A,[HL]
1
6
A
←
A
∨
(HL)
×
XOR
A,[HL+byte]
2
6
A
←
A
∨
(HL+byte)
×
Remark
One instruction clock cycle is one CPU clock cycle (f
CPU
) selected by processor clock control register
(PCC).
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