CHAPTER 6 16-BIT TIMER
User's Manual U11919EJ3V0UM00
101
6.4.2 Operation as timer output
Timer outputs are repeatedly generated at the count value set to 16-bit compare register 20 (CR20) in advance
based on the intervals of the value set in TCL201 and TCL200.
To operate the 16-bit timer as a timer output, the following settings are required.
•
Set P51 to output mode (PM51 = 0).
•
Set 0 to the output latch of P51.
•
Set the count value in CR20.
•
Set 16-bit timer mode control register 20 (TMC20) as shown in Figure 6-6.
Figure 6-6. Settings of 16-Bit Timer Mode Control Register 20 at Timer Output Operation
-
0/1
0/1
0/1
1
0
0/1
1
TOD20 TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
TMC20
TO20 Output Enable
Setting of Count Clock (see Table 6-2)
Inverse Enable of Timer Output Data
Caution
If both CPT201 flag and CPT200 flag are set to 0, the capture edge becomes operation
prohibited.
When the count value of 16-bit timer counter 20 (TM20) matches the value set in CR20, the output status of the
TO2/P51 pin is inverted. This enables timer output. At that time, TM20 count is continued and an interrupt request
signal (INTTM2) is generated.
Figure 6-7 shows the timing of timer output (see Table 6-2 for the interval time of the 16-bit timer).
Figure 6-7. Timer Output Timing
Count Clock
TM20 Count Value
CR20
INTTM2
TO20
Note
TOF20
0000H
0001H
N
FFFFH 0000H
0001H
N
FFFFH
N
N
N
N
N
Interrupt Accepted
Interrupt Accepted
Overflow Flag Set
t
Note
The TO20 initial value becomes low level during output enable (TOE20 = 1).
Remark
N = 0000H to FFFFH
Содержание mPD789026 Subseries
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