CHAPTER 4 DIFFERENCES BETWEEN TARGET DEVICE AND TARGET INTERFACE CIRCUIT
User’s Manual U16499EJ1V0UM
33
(2) Signals input from the target system via a gate
Since the following signals are input via a gate, their timing shows a delay compared to the
µ
PD789052, 789062,
789860, and 789861 Subseries. Refer to
Figure 4-2 Equivalent Circuit 2 of Emulation Circuit
.
• RESET signal
• Signals related to clock input
The X2 (CL2) pin is not used in the IE-789860-NS-EM1.
Figure 4-2. Equivalent Circuit 2 of Emulation Circuit
•
Probe side
(Target system)
•
IE system side
(IE-789860-NS-EM1)
100
Ω
100
Ω
LV
CC
1 M
Ω
4.7 k
Ω
HSK120
HSK120
X1
RESET
X1 (CL1)
X2 (CL2)
RESET
OPEN
HC4066
LV
CC
Содержание IE-789860-NS-EM1
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