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Preliminary User’s Manual U16345EE1V0UM00
Chapter 3
Operating Precautions
Be aware of the following operating precautions when using the IE-703242-G1-EM1.
3.1 Reset source monitor flag
The reset source (reset caused by external reset input or watchdog timer) can not be distinguished by
the RSM register of the clock controller during emulation mode. Oscillation stabilization time is skipped
after a watchdog timer reset during sub watch mode.
3.2 Standby
release
The main oscillator of the V850ES/GB1 I/O chip on the emulation board is always running and can not
be switched off. Therefore no oscillation stabilization time is required when stop mode or sub watch
mode of V850ES/GB1 is released. As a consequence of this the V850ES/GB1 I/O chip on the ICE will
wake up immediately from sub watch or stop mode whereas the V850ES/GB1 real chip always assures
the oscillation stabilization time for the main oscillator when standby mode is released.
3.3 Port direction setting for peripheral function
When a peripheral function is used the direction setting for the respective port bit of the V850ES/GB1
real chip is not set automatically. The port bit direction has to be programmed according to the
requirement of the peripheral function by setting the port mode register. In the FPGA on the emulation
board port mode setting is not necessary when a peripheral function is used. Therefore on the emulator
ports emulated by the FPGA behave different from the real chip. This only affects bit 1 of port PCM,
CLOCKOUT function. Therefore if the CLOCKOUT function is to be used the respective bit positions of
registers PMCM and PMCCM have to be set accordingly.
3.4 Programmable peripheral area
The usable settings for the BPC register limit usage to the first 32MB of the total address range. There-
fore the programmable peripheral area must be set to an address range within the first 32 MB.
3.5 Other
precautions
Take note of the differences between the In-Circuit Emulator and the real chip described in
Chapter 4
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