NEC IE-703003-MC-EM1, Предварительное руководство пользователя

Страница: 23 / 28

CHAPTER 3 CAUTIONS
12
3.3 NMI Signal
The NMI signal from the target system is delayed because it passes through VHC32 before being input into the IE-
703003-MC-EM1. (t
pLH
= t
pHL
= 8 ns (TYP.))
Moreover, DC characteristics are changed to input voltage V
IH
= 0.7 V
DD
(MIN.), V
IL
= 0.3 V
DD
(MAX.), input current
I
IN
=
±
1.0
µ
A (MAX.).
Figure 3-1. NMI Signal-Flow Path
IE-703003-MC-EM1
Target system
NMI signal
NMI pin VHC32 I/O device
3.4 X1 Signal
The X1 signal from the target system is delayed because it passes through VHCT08 before being input into the
evaluation chip of the IE-703003-MC-EM1. (t
pLH
= 8 ns (MAX.), t
pHL
= 9 ns (MAX.))
Moreover, DC characteristics are changed to input voltage V
IH
= 2.0 V (MIN.), V
IL
= 0.8 V (MAX.), input current I
IN
=
±
1.0
µ
A (MAX.).
Figure 3-2. X1 Signal-Flow Path
IE-703003-MC-EM1
Target system
X1 signal
X1 pin VHCT08 Evaluation chip