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SP16160CH1RB Reference Design Board User’s Guide
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recommended. Using only a lowpass filter is not
recommended as the SNR performance is significantly
degraded by the broad-band signal generator noise in
the passband.
6.2 IF-Sampling Sub-System Frequency Plan
The SP16160CH1RB sub-samples the 192 MHz IF
with a 153.6 MSPS clock so that the 20 MHz signal
band aliases to the center of the first Nyquist zone at
38.4 MHz.
A large benefit of this plan is the placement of of the
second order harmonic, H2, completely out of the band
of interest when it aliases. H3 cannot be excluded from
the signal band and must be reduced in the system as
much as possible. The frequency ranges of the H2 and
H3 aliases are shown in Figure 8.
6.3 ADC Reference
The SP16160CH1RB reference board is configured to
use the internal 1.2V reference on the ADC16DV160.
This is the recommended reference configuration for
the ADC16DV160.
The ADC has an internal register option to reduce the
reference voltage for improved distortion at the cost of
reduced SNR. The register can be configured using the
WaveVision 5 data capture platform.
6.4 Clock Path
The clock signal used to sample the analog input is
generated using the LMK04031B. The LMK04031B is a
low-jitter precision clock conditioner that consists of
cascaded phase locked loops (PLLs), an internal
voltage controlled oscillator (VCO) and a distribution
stage. The first PLL locks an external voltage controlled
crystal oscillator (VCXO) to an incoming reference
clock and filters the phase noise of the reference. The
output of the first PLL becomes the reference input to
the second PLL stage which uses a VCO to multiply the
external VCXO frequency. The VCO output is passed
to the distribution stage which provides frequency
division, buffering and conversion to a number of clock
output formats including CMOS, LVPECL and LVDS.
For a lower cost implementation, the first PLL can also
be configured to use an internal, low-noise oscillator
circuit with an external crystal and varactor diode.
In the SP16160CH1RB system shown in Figure 9, the
clock is generated with the LMK04031B by locking a
76.8 MHz VCXO (Crystek CVHD-950-76.8) to the
61.44 MHz reference oscillator, cleaning the phase
noise, multiplying the VCXO to 1536 MHz and then
dividing the frequency down to output a 153.6 MHz,
single-ended CMOS clock. The external loop filter
components for PLL1 and PLL2 are optimized for low
jitter performance.
The single-ended CMOS clock signal from the
LMK04031B is passed through a narrow bandwidth
SAW filter and then buffered with a low-noise CMOS
buffer to create a very low jitter, single-ended clock
source at the CLK+ input of the ADC16DV160. Filtering
[MHz]
20 MHz
38.4
H2
H3
IF Band
Figure 8: Frequency plan showing aliasing of
the 192 MHz IF band, H2 band, and H3 band
into the first Nyquist zone
76.8
Figure 9: Sampling clock path of the SP16160CH1RB
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