5
4
1
2
3
6
J1
4
1
2
3
J5
5
4
1
2
3
6
J2
5
4
1
2
3
6
J3
5
4
1
2
3
6
J6
1
2
3
4
5
6
7
8
9
10
J4
AGND
D2
CFLY1
C3
CFLY2
A3
ENN
A1
ENP
B1
OUTP
E3
OUTN
A2
PGND
B3
PGND
E1
REG
D3
REG
E2
SCL
B2
SDA
C2
SW
D1
VIN
C1
U1
TPS65132LYFFR
4.7µF
C3
4.7µF
C4
4.7µF
C5
2.2µF
C2
GND
GND
GND
GND
GND
GND
GND
GND
GND
4.7µF
C1
GND
OUTP
OUTN
REG
VIN
CFLY1
CFLY2
SW
VIN
2.5V to 5.5V
S+
GND
ON
ENP/EN
OFF
ON
ENN/SYNC/ /WP
OFF
VPOS
S+
GND
VNEG
S-
GND
REG
GND
GND
1
2
3
JP2
1
2
3
JP1
L1
4.7uH
VIN
VIN
TP4
4 V to 6 V
-6 V to -4 V
TP2
TP3
TP1
Schematic
4
SLVUAO0 – February 2016
Copyright © 2016, Texas Instruments Incorporated
TPS65132L Evaluation Module
3
Schematic
is for reference only; see the bill of materials in
for specific values.
Figure 1. Schematic