20205203
Horizontal Resolution: 50 ms/div.
Trace 1: PoE input voltage across the VIN and VEE pins. 20V/div.
Trace 2: Voltage across the RTN and VEE pins, namely the voltage across
the Hot Swap MOSFET. 20V/div.
Trace 3: The input current. 0.2A/div.
Trace 4: The 3.3V output voltage. 2V/div.
FIGURE 5. PoE Power Up Sequence with a Midspan PSE
AUXILIARY INPUT POWER UP SEQUENCE
The AUX input power up sequence is simpler:
1.
AUX power application quickly charges the input
capacitors. The AUX input inrush limit resistors limit the
inrush current and prevent any overshoot of the voltage
across the VIN and RTN pins.
2.
When the VCC regulator starts up, the PWM controller
begins soft start.
3.
After soft start, the switching regulator achieves output
regulation, and the converter enters steady state
operation. The auxiliary winding will raise the VCC
voltage to about 10.5V, thus shutting down the internal
regulator and increasing efficiency.
Figure 6 shows key waveforms during a normal AUX power
up sequence.
20205204
Horizontal Resolution: 5 ms/div.
Trace 1: AUX input voltage (VIN to RTN pins). 10V/div.
Trace 2: The 3.3V output voltage. 2V/div.
Trace 3: The input current. 1A/div.
FIGURE 6. AUX Power Up Sequence
OUTPUT DEAD SHORT FAULT RESPONSE AND OVER
CURRENT PROTECTION
The evaluation board survives the output dead short condition
by running into re-try mode (hiccup) or cycle-by-cycle peak
current limit mode, depending on the input voltage condition
when the fault occurs. Applying a dead short to the +3.3V line
causes a number of protection mechanisms to take place se-
quentially. They are:
1.
The feedback signal increases the duty cycle in an
attempt to maintain the output voltage. This initiates
cycle-by-cycle over-current limiting which turns off the
main switch when the current sense (CS) pin exceeds
the current limit threshold.
2.
The current in the internal hot swap MOSFET increases
until it is current limited around 800 mA. Some overshoot
in the current will be observed, as it takes time for the
current limit amplifier to react and change the operating
mode of the MOSFET.
3.
Because linear current limiting is accomplished by
driving the MOSET into the saturation region, the drain
voltage (RTN pin) rises. When it reaches 2.5V with
respect to VEE, power good is de-asserted and the
nPGOOD pin voltage rises.
4.
The de-assertion of power good causes the discharge of
the soft-start capacitor, which disables all switching
action in the dc-dc converter.
5.
Once the switching stops, the current in the internal
MOSFET will decrease and the drain voltage will fall back
below 1.5V with respect to VEE. When power good is re-
asserted, the dc-dc converter will automatically restart
with a new soft-start sequence.
Figure 7 and Figure 8 show cycle-by-cycle peak current limit
in response to an output dead short with a 24V AUX input and
48V PoE input, respectively. The short-circuit condition re-
sults in a peak current of about 3.2A in the primary circuit. This
peak current produces about 0.5V peak at the CS pin, initiat-
ing cycle-by-cycle peak current limit mode. The duty cycle is
thus greatly reduced, which in turn limits the AUX input dc
current to about 0.39A, and the PoE input dc current to about
0.16A, respectively.
20205205
Horizontal Resolution: 1 µs/div.
Trace 1: Current sense voltage across RE15. 0.5V/div.
Trace 2: The input current from the AUX power source. 200 mA/div
FIGURE 7. Cycle-by-cycle Peak Current Limit under AUX
Input and Output Dead Short Condition
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