3.0 Functional Description
(Continued)
15
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DP83816
Figure 3-4 DSP Physical Layer Block Diagram
TRANSMIT CHANNELS &
100 MB/S
10 MB/S
NRZ TO
MANCHESTER
ENCODER
STATE MACHINES
TRANSMIT
FILTER
LINK PULSE
GENERATOR
4B/5B
ENCODER
SCRAMBLER
PARALLEL TO
SERIAL
NRZ TO NRZI
ENCODER
BINARY TO
MLT-3
ENCODER
10/100 COMMON
RECEIVE CHANNELS &
100 MB/S
10 MB/S
MANCHESTER
TO NRZ
DECODER
STATE MACHINES
RECEIVE
FILTER
LINK PULSE
DETECTOR
4B/5B
DECODER
DESCRAMBLER
SERIAL TO
PARALLEL
NRZI TO NRZ
DECODER
MLT-3 TO
10/100 COMMON
AUTO-NEGOTIATION
STATE MACHINE
FAR-END-FAULT
STATE MACHINE
REGISTERS
AUTO
100BASE-X
10BASE-T
MII
BASIC MODE
PCS CONTROL
PHY ADDRESS
NEGOTIATION
CLOCK
CLOCK
RECOVERY
CLOCK
RECOVERY
CODE GROUP
ALIGNMENT
SMART
SQUELCH
RX_DATA
RXCLK
RX_DATA
RXCLK
TX_DATA
TX_DATA
TXCLK
SYSTEM CLOCK
REFERENCE
RD
±
TD
±
OUTPUT DRIVER
INPUT BUFFER
BINARY
DECODER
ADAPTIVE
EQ
AND
BLW
COMP.
(ALSO FX_RD
±)
LED
DRIVERS
LEDS
POWER ON
CONFIGURATION
PINS
GENERATION
CONTROL
NCL
K_50M
TXC
L
K
TXD(
3:0)
TXER
TXEN
MDIO
MDC
COL
CRS
RXEN
RXER
RXDV
RXD(
3:0)
RXCL
K
MAC INTERFACE
SERIAL
MANAGEMENT
Содержание MacPHYTER-II DP83816
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