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National Semiconductor DP8400, Примечание к применению

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MICROPROCESSOR INTERFACE CIRCUITS

The major 8-bit, 16-bit and 32-bit microprocessors have dif-
ferent control signal timing. There are also a number of
speed options. The DP8400 family was designed, not for a
specific microprocessor, but rather, significant control flexi-
bility has been provided on both the DP84XX DRAM control-
ler/drivers and the DP84XX error correction devices for
easy interface to any microprocessor. However, a certain
amount of ‘‘glue’’ is necessary to interface to these LSI cir-
cuits, usually in the form of a number of MSI/SSI logic cir-
cuits. Not only can this be costly in board space utilization,
but it is usually the one place where the most design related
problems occur in system development.

Figures 13 and 14 show the DP8400 family solution to this

problemÐthe DP84XX2 series of microprocessor interface
circuits.

Figure 13 shows how the DP84300 refresh timer

and the DP84XX2 microprocessor interface circuit connect
to the DP8409A and various microprocessors for a typical
application.

Figure 14 shows the DP8409A and the DP8400

together in a microprocessor-based memory system using
DRAMs, with double bit error detect and single bit error cor-
rect capability. In addition, it shows that with the simple ad-
dition of some standard data buffers, how the system can
implement byte writing to the DRAM array.

This system structure requires the insertion of few or no wait
states during a memory access cycle, thus maximizing
throughput. The DP84XX2 circuits have been designed to
work with all of National’s DRAM controller/drivers to con-
trol refreshing so that system throughput is affected only
when absolutely necessary. First, in any refresh clock peri-
od of 16

m

s, hidden refreshing is given maximum opportuni-

ty. This can be helped with the optional DP84300 refresh
interval generator which offers maximum high-to-low ratio-
ing of RFCK. Second, when a hidden refresh does not occur
in a particular RFCK cycle, a forced refresh may still not
affect a slow access cycle. The worst-case is when an ac-
cess is pending during a forced refresh, in which case a
three wait state delay is usually the maximum penalty.

Usually two DP84XX2 type chips would be required to inter-
face between any microprocessor and the DP8400/
DP8409A combined system. These chips would handle the
read/write control as well as error detection and correction
control. Table VII shows the individual DP84XX2 circuits
that would be used in systems with no error correction, thus
requiring only the DP84XX DRAM controller/driver function.

²

The select wait input to the
DP843X2 chip inserts a wait
state during accessing. This is
necessary for very fast micro-
processors.

TL/F/5012 – 17

FIGURE 13. Connecting the DP8409A between 16-Bit Microprocessor and Memory

11

Содержание DP8400

Страница 1: ... dynamic RAM controller driver was the first controller to resolve all of these problems This Schottky bipolar device provides the flexibility of external access control along with automatic access timing genera tion without the need for an external timing generator clock In addition on board capacitive drivers allow direct drive for over 88 DRAMs With the simple addition of refresh clocks the cir...

Страница 2: ...nal clock is required On chip delays insure proper address and control sequenc ing once the valid parallel address is presented to the fall through input latches of the DP8409A When the RASIN transitions high to low the decoded RAS output transitions low strobing the row address into the DRAM array An on chip delay automatically generates a guaranteed selectable mode 5 or 6 row address hold time A...

Страница 3: ...ershoot undershoot at memories TL F 5012 2 FIGURE 2 Typical Application of DP8409A Using External Control and Refresh in Modes 0 and 4 TL F 5012 3 FIGURE 3 This figure demonstrates the automatic accessing capability of the DP8409A Only one strobing edge RASIN is required for generation of all DRAM access timing signals This is accomplished with on chip delay generators eliminating the need for ext...

Страница 4: ...sition Thesystemisnotifiedafterthenega tive going RFCK transition that a hidden refresh has not oc curred via the refresh request output RF I O pin The sys tem acknowledges the request for a forced refresh by set ting M2 refresh low on the DP8409A and preventing fur ther access to the DP8409A The DP8409A then uses RGCK to generate an automatic forced refresh The refresh request pin then returns to...

Страница 5: ... a reasonable level as demonstrated by the graphs shown in Figures 7a 7b of power versus frequency The DP84240 and the DP84244 are fabricated on a high performance oxide isolated Schottky bipolar process Spe cial circuit techiques have been used to minimize internal delays and skews Additionally both rise and fall time char acteristics track closely as a function of load capacitance This has been ...

Страница 6: ...to input pulse distortion ERROR CORRECTION The determination of whether a DRAM system requires er ror correction must be resolved early in the system design A positive answer to this question may have far reaching impact on board development time and component cost It is clear however that such a decision cannot be taken lightly The type and origin of errors in DRAM systems are many and can result...

Страница 7: ... read memory access cycles Figure 9a shows the normal write cycle where system data is used by the DP8400 to generate parity bits called check bits based on certain combinations of the data bits This combination is defined by the DP8400 s matrix shown in Figure 10 When ever a 1 occurs in any row the corresponding input data bit at the top of the column helps determine the parity for that check bit...

Страница 8: ...P8400 TL F 5012 12 FIGURE 9b Normal Read Mode Using the Error Monitoring Method with the DP8400 TL F 5012 13 FIGURE 9c Normal Read Mode Using the Always Correct Method with the DP8400 C2 C3 generate odd parity TL F 5012 14 FIGURE 10 DP8400 Matrix 8 ...

Страница 9: ...ould not be quickly found The occurrence of a double error comprising one soft and one hard must now be considered This type of error has a higher probability than two soft errors The hard error may be due to a catastrophic chip failure and a subsequent soft error will create two errors This can be a source of concern since most error correction chips cannot handle double er rors of this type Ther...

Страница 10: ...n the system to warn the operator that the system is in a degrad ed operational mode and that field service should occur shortly In the meantime the system will continue to operate properly The key to the effectiveness of the DP8400 in this application is its three error flags which allow complete error reportingÐincluding a unique double error indication DP8402A 3 4 5 32 Bit Error Detector and Co...

Страница 11: ... the system can implement byte writing to the DRAM array This system structure requires the insertion of few or no wait states during a memory access cycle thus maximizing throughput The DP84XX2 circuits have been designed to work with all of National s DRAM controller drivers to con trol refreshing so that system throughput is affected only when absolutely necessary First in any refresh clock per...

Страница 12: ...urers CPU enjoying a favorite role Data sheets and more detailed application information are available for all the members of the DP8400 family Contact your local National Semiconductor representative or Nation al Semiconductor directly TL F 5012 18 FIGURE 14 Flexible Application of the DP8409A and DP8400 This Figure Shows an Application with a 16 Bit Microprocessor TABLE VII The DP84300 Series of...

Страница 13: ...13 ...

Страница 14: ...h instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 Email cnjwge tevm2 ...

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