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TL/F/5012

The

DP8400

Family

of
Memory

Interface

Circuits

AN-302

National Semiconductor
Application Note 302
Charles Carinalli
Mike Evans
February 1986

The DP8400 Family of
Memory Interface Circuits

INTRODUCTION

The rapid development in dynamic random access memory
(DRAM) chip storage capability, coupled with significant
component cost reductions, has allowed designers to build
large memory arrays with high performance specifications.
However, the development of memory arrays continues to
have a common set of problems generated by the complex
timing and refresh requirements of DRAMs. These include:
how to quickly drive the memories to take advantage of their
speed, minimization of board space required by the support
circuitry and the need for error detection and correction.
Unfortunately, these problems must be addressed with each
new system design. Full system solutions will vary greatly,
depending on the DRAM array size, memory speed, and the
processor.

This application note introduces a complete family of DRAM
support circuits that provides a straightforward solution to
the above problems while allowing a high degree of flexibili-
ty in application with little or no performance penalty. The
DP8400 family (Table I) includes DRAM controllers, error
detection/correction circuits, octal address buffers and sys-
tem control circuits. The LSI blocks are designed with flex-
ible interfaces, making application possible with all existing
DRAMs including the recently announced 1 Mbit devices.
Additionally, interface is easy to all popular microprocessors
with memory word widths possible from 8 to 80 bits.

TABLE I. DP8400 Family Members

DP8400-2,

16 and 32 Bit Error

DP8402A

Checker/Correctors

DP8408A, DP8409A,

DRAM Controller/Drivers

DP8417, DP8418,
DP8419, DP8428, DP8429

DP8420, DP84244

DRAM Buffer Drivers

DP84XX2

Microprocessor
Interface Circuits

FULL FUNCTION DRAM CONTROLLER

The heart of any DRAM array design is the controller func-
tion. Previous LSI controllers supplied a minimum function
of address multiplexing with an on-board refresh counter.
This required external delay line timing and logic to control
memory access, additional logic to perform memory refresh,
and external drivers to drive the capacitive memory array.
The complete solution results in significant access delay in
relation to DRAM speeds and skews in output sequencing,
as well as a large component count.

A previous LSI solution brought much of this logic on-chip.
However, it is limited in application to certain microproces-
sors and has the disadvantage of all access timing originat-
ing from an external clock, whose phase uncertainty gener-
ates a delay in actually knowing when an access has start-
ed.

The DP8409A multi-mode dynamic RAM controller/driver
was the first controller to resolve all of these problems. This
Schottky bipolar device provides the flexibility of external
access control, along with automatic access timing genera-
tion, without the need for an external timing generator clock.
In addition, on-board capacitive drivers allow direct drive for
over 88 DRAMs. With the simple addition of refresh clocks,
the circuit can perform hidden refresh automatically. It is the
DP8409A design that has been used as the spring board for
a whole family of controllers with faster speed performance
while maintaining maximum pin upgrade compatibility.

All Control On-Chip

Figure 1 is a block diagram of the DP8409A. the ADS input

strobes the parallel memory address into the row latches
R0 – 8, the column latches C0 – 8, and bank select B0 and
B1. The nine output drivers may be multiplexed between the
row or column input latches, or the 9-bit on-chip refresh
counter. One of four RAS outputs is selected during an ac-
cess cycle by setting the bank select inputs B0 or B1. All
four RAS outputs are active during refresh. Either external
or automatic control is available on-chip for the CAS output,
while an on-chip buffer is provided to minimize skew associ-
ated with WE output generation.

All DRAM address and control outputs on the DP8409A can
directly drive in excess of 500 pF, or the equivalent of 88
DRAMs (4 banks of 22 DRAMs). All output drivers are
closely matched, significantly reducing output skew. Each
output stage has symmetrical high and low logic level drive
capability, insuring matched rise and fall time characteris-
tics.

Flexibility and Upgradability to 256k or 1 Mbit DRAMs

The 9 multiplexed address outputs and 9-bit internal refresh
counter of the DP8409A direct addressing capability for
256k DRAMs. Careful design of memory boards, using 64k
DRAMs with the DP8409A, insures direct upgradability to
256k DRAMs. This can be done by simply allowing for board
address extension by two bits and designing the ninth ad-
dress trace (Q8) of the DP8409A to connect to pin 1 of the
DRAMs (A8). This is, in general, a non-connected pin in
64ks and the ninth address in 256ks. All that need be done
is to remove the 64ks and replace them with 256ks, thereby
increasing the memory on the same board by a 4 to 1 ratio.
The resulting development cost saving can be significant.

Although the new 1 Mbit DRAMs require the larger 18 pin
package, which will require a memory board redesign, up-
grading the controller portion of the board may need no
redesign when converting from the DP8409A or DP8419 to
the new DP8429 1 Mbit DRAM controller driver.

Three mode pins (M0, M1 and M2) offer externally select-
able modes of operation, a key reason for the DP8409A’s
application flexibility (Table II). The operational modes are
divided between external and automatic memory control.

C

1995 National Semiconductor Corporation

RRD-B30M115/Printed in U. S. A.

Содержание DP8400

Страница 1: ... dynamic RAM controller driver was the first controller to resolve all of these problems This Schottky bipolar device provides the flexibility of external access control along with automatic access timing genera tion without the need for an external timing generator clock In addition on board capacitive drivers allow direct drive for over 88 DRAMs With the simple addition of refresh clocks the cir...

Страница 2: ...nal clock is required On chip delays insure proper address and control sequenc ing once the valid parallel address is presented to the fall through input latches of the DP8409A When the RASIN transitions high to low the decoded RAS output transitions low strobing the row address into the DRAM array An on chip delay automatically generates a guaranteed selectable mode 5 or 6 row address hold time A...

Страница 3: ...ershoot undershoot at memories TL F 5012 2 FIGURE 2 Typical Application of DP8409A Using External Control and Refresh in Modes 0 and 4 TL F 5012 3 FIGURE 3 This figure demonstrates the automatic accessing capability of the DP8409A Only one strobing edge RASIN is required for generation of all DRAM access timing signals This is accomplished with on chip delay generators eliminating the need for ext...

Страница 4: ...sition Thesystemisnotifiedafterthenega tive going RFCK transition that a hidden refresh has not oc curred via the refresh request output RF I O pin The sys tem acknowledges the request for a forced refresh by set ting M2 refresh low on the DP8409A and preventing fur ther access to the DP8409A The DP8409A then uses RGCK to generate an automatic forced refresh The refresh request pin then returns to...

Страница 5: ... a reasonable level as demonstrated by the graphs shown in Figures 7a 7b of power versus frequency The DP84240 and the DP84244 are fabricated on a high performance oxide isolated Schottky bipolar process Spe cial circuit techiques have been used to minimize internal delays and skews Additionally both rise and fall time char acteristics track closely as a function of load capacitance This has been ...

Страница 6: ...to input pulse distortion ERROR CORRECTION The determination of whether a DRAM system requires er ror correction must be resolved early in the system design A positive answer to this question may have far reaching impact on board development time and component cost It is clear however that such a decision cannot be taken lightly The type and origin of errors in DRAM systems are many and can result...

Страница 7: ... read memory access cycles Figure 9a shows the normal write cycle where system data is used by the DP8400 to generate parity bits called check bits based on certain combinations of the data bits This combination is defined by the DP8400 s matrix shown in Figure 10 When ever a 1 occurs in any row the corresponding input data bit at the top of the column helps determine the parity for that check bit...

Страница 8: ...P8400 TL F 5012 12 FIGURE 9b Normal Read Mode Using the Error Monitoring Method with the DP8400 TL F 5012 13 FIGURE 9c Normal Read Mode Using the Always Correct Method with the DP8400 C2 C3 generate odd parity TL F 5012 14 FIGURE 10 DP8400 Matrix 8 ...

Страница 9: ...ould not be quickly found The occurrence of a double error comprising one soft and one hard must now be considered This type of error has a higher probability than two soft errors The hard error may be due to a catastrophic chip failure and a subsequent soft error will create two errors This can be a source of concern since most error correction chips cannot handle double er rors of this type Ther...

Страница 10: ...n the system to warn the operator that the system is in a degrad ed operational mode and that field service should occur shortly In the meantime the system will continue to operate properly The key to the effectiveness of the DP8400 in this application is its three error flags which allow complete error reportingÐincluding a unique double error indication DP8402A 3 4 5 32 Bit Error Detector and Co...

Страница 11: ... the system can implement byte writing to the DRAM array This system structure requires the insertion of few or no wait states during a memory access cycle thus maximizing throughput The DP84XX2 circuits have been designed to work with all of National s DRAM controller drivers to con trol refreshing so that system throughput is affected only when absolutely necessary First in any refresh clock per...

Страница 12: ...urers CPU enjoying a favorite role Data sheets and more detailed application information are available for all the members of the DP8400 family Contact your local National Semiconductor representative or Nation al Semiconductor directly TL F 5012 18 FIGURE 14 Flexible Application of the DP8409A and DP8400 This Figure Shows an Application with a 16 Bit Microprocessor TABLE VII The DP84300 Series of...

Страница 13: ...13 ...

Страница 14: ...h instructions for use provided in the labeling can effectiveness be reasonably expected to result in a significant injury to the user National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd Japan Ltd 1111 West Bardin Road Fax a49 0 180 530 85 86 13th Floor Straight Block Tel 81 043 299 2309 Arlington TX 76017 Email cnjwge tevm2 ...

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