National Semiconductor Data Capture Board CLC-CAPT-PCASM Скачать руководство пользователя страница 11

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** From the Windows Start Programs menu, 

launch

the Capture program (it’s inside the C:\nsc folder).
Right click inside the Control Panel and select
Configure I/O and click the appropriate PC COM
port button. Next, right click inside the Control Panel
and select 

Configure Capture. Select the following

options: 

Mode = Capture; Bits =24; Channel = A;

From = AOUT; 1st Bit = Capture 1st Bit; Phase =
In Phase Only
. Click “OK” and then click the Start
button in the Control Panel to start the data capture.
The progress bar should conclude in about 10 seconds. 

** Launch Matlab. Use the Matlab path browser to

include the analysis Mfiles. The installed default
path is: “c:\nsc\mfiles”. Add this to the Matlab paths,
save the directory file and exit the path browser. At
the Matlab command line enter “analysis_menu”. A
GUI will appear. Left click on the 

DRCS_Serial but-

ton to perform an FFT on the captured data. 

The menu disappears while the analysis routine is
running. The process takes 4 - 5 seconds on a 133MHz
PC and plots the results when finished.

The FFT should report an input power of about -18dBFS.

The FFT plot above and the analysis results highlight
several setup issues. The poor SINAD (and correspond-
ing ENOB) is due to phase jitter (spec’d as SSB Phase
Noise) of the IF signal source (an HP8656 was used
here). A better choice of signal synthesizer is the
HP8644B, which yields a SINAD of about 60dB under the
same conditions. The main portion of the noise power is
contained in the carrier’s immediate sidebands (±5KHz).

Another point of interest is that there are several spectral
lines about -75dBFS and 25KHz on either side of the
fundamental. These have been traced to the ground loop
created by the PC serial interface. Both serial interface
cables were connected while this data was being
collected. Removing the cable to the DRCS will reduce
the amplitude of these spurs. Some of the ground loop
remains because of the required Capture Board’s serial
interface to the PC.

Section IV. Data Analysis Tools

The Matlab scripts contained on the Evaluation Kit
CDROM provide a convenient toolset for evaluation of
National’s Diversity Receiver ChipSet (DRCS) and high
speed ADCs like the CLC595x family. There are 4 FFT
routines and 1 Sine Histogram routine which can be
called from a user interface menu, “analysis_menu”. Set
the Matlab path and working directory to that of the
“Mfiles” provided on the Evaluation Kit CDROM. Run
“analysis_menu” from the Matlab command window
to open a graphical user interface. Each of the called FFT
routines has its appropriate variables set prior to the data
analysis. These variables are explained in the adjacent
text and can be easily edited to adjust for a particular
application from Matlab’s script editor. There are also
comments within the routines that highlight various
analysis blocks.

2

4

6

8

10

12

x 10

4

-160

-140

-120

-100

-80

-60

-40

-20

Frequency

Magnitude (dBFS)

32768 Point FFT Analysis

Pinput (dBFS) = -18.1087

Output SINAD = 51.7058

Output SFDR = 56.0663

THD (dBFS) = -100.7444

 E

n

 floor = -69.448

ENOB = 11.302

Содержание Data Capture Board CLC-CAPT-PCASM

Страница 1: ...Receiver Transmitter an oscillator and a level translator IC The captured data is stored in either three 32K x 8 static RAMs organized into 24 bit words or in a FIFO containing 32K 18 bit words LEDs...

Страница 2: ...n board An amplitude of 10 to 16dBm is recommended Here again the HP 8644B is a good choice Software 1 National Semiconductor Software All of the required software is provided on a CD ROM To install t...

Страница 3: ...on board pin 20B The third jumper block J2 is unused Data Capture Board Block Diagram DIP Switches Five of the eight DIP switches are used to configure several capture functions as follows DIP switch...

Страница 4: ...e Data Capture Board is powered up and the FPGA is initialized it is on to indicate that the board is ready After all the SRAM data has been output it is off LED 2 This LED is on when captured data is...

Страница 5: ...ou start with the default file name and location shown Click on Default and then on OK If you do not have a C temp directory please make one The reason for this is that the Matlab script files for dat...

Страница 6: ...configuration menu Select Histogram Debug as shown above and click on OK When the data capture control panel returns you can verify your capture settings by positioning the mouse over the progress bar...

Страница 7: ...and Capture Board combination require 5V at 1A 4 An IBM Compatible Personal Computer running Windows 95 Windows 98 or Windows NT with a serial port capable of 115 200 baud 5 Serial data cable to conne...

Страница 8: ...on The SRAM is useful for displaying time records of data or collecting contiguous blocks of slower data that have been decimated by the CLC5902 DDC The SRAM is the memory element used for the board s...

Страница 9: ...rted Next is a discussion of the Mode functions and the related sub functions MODES There are four primary modes in which to run the data capture system each with its own associated options 1 Capture...

Страница 10: ...ta source The DRCS Debug data will be displayed at the 15 bit resolution limit this is also the case for the DRCS 24 bit Serial Out data and the histogram will be centered about 16 384 assuming there...

Страница 11: ...ditions The main portion of the noise power is contained in the carrier s immediate sidebands 5KHz Another point of interest is that there are several spectral lines about 75dBFS and 25KHz on either s...

Страница 12: ...variable to 0 Setting the Dither variable excludes a lower portion of the spectrum from the FFT analysis and is intended to be used in conjunction with a base band dither signal being present at the...

Страница 13: ...13 http www national com CLC CAPT PCASM Evaluation Board Layer 1 CLC CAPT PCASM Evaluation Board Layer 2 CLC CAPT PCASM Evaluation Board Layer 3 CLC CAPT PCASM Evaluation Board Layer 4...

Страница 14: ...1 1 1 1 6 287 287 287 1 9 9 1 1 1 1 1 1 1 6 6 287 9 9 9 9 5 9 9 9 9 1 4 5 2 2 5 1 57 4 4 9 4 3 3 1 1 5 5 1 2 9 1 4 1 4 602 9 4 1 4 4 4 4 4 4 9 4 4 1 4 4 1 4 56 1 1 1 1 1 865 21 B 21 6 7 7 7 7 7 7 7 7...

Страница 15: ...o perform can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor National Semiconductor National Semicondu...

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