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National Semiconductor ADC12V170 Скачать руководство пользователя страница 6

ADC12V170 Evaluation Board User’s Guide 

N

 

- 6 -  

www.national.com 

Rev 0.0

 

…,  D11+/-)  being  emitted  with  one  clock  edge  during 
the first half of the clock period and the other half of the 
data (even bits: D0+/-, D2+/-, …, D10+/-) being emitted 
with the opposite clock edge during the second half of 
the clock period.  The odd data bits should be captured 
with  the  falling  edge  of  DRDY  and  the  rising  edge  of 
DRDY  should  be  used  to  capture  the  even  bits  of  the 
data. 

The  data  is  available  on  the  evaluation  board  at  pins 
A5/B5  (MSB  +/-)  through  A10/B10  (LSB  +/-)  of  the 
FutureBus  connector  (schematic  reference  designator 
FB).    Please  keep  in  mind  that  because  the  data  is  in 
DDR  format,  pins  A5/B5  will  carry  data  bit  D11+/- 
during the first half of the clock period and these lines 
will carry bit D10+/- during the second half of the clock 
period.    Similarly,  pins  A10/B10  will carry D1+/- during 
the first half of the clock period and these pins will carry 
D0+/-  during  the  second  half  of the clock period.  The 

DRDY signal which is used to capture the data is also 
in  LVDS  format  and  it  is  available  at  pins  A4/D4 
(DRDY+/-)  on  the  FutureBus  connector.    The  over-
range  bit  (OVR)  LVDS  signal  is  available  on  pins 
D22/D21 (OVR+/-) on the FutureBus connector. 

Please see the Evaluation Board schematic in Section 
5.0 and the ADC12V170 datasheet for further details. 

4.5 Power requirements. 

Power to the ADC12V170 evaluation board is supplied 
through  the  green  power  connector  labeled  “+5V” 
which  is  located  along  the  bottom  edge  of  the  board. 
Voltage and current requirements are: 

•

  +5V capable of providing up to 500mA (ADC12V170 

evaluation board only) 

 

Содержание ADC12V170

Страница 1: ...N www national com Rev 0 0 October 2007 Evaluation Board User s Guide for ADC12V170 12 Bit 170 MSPS Analog to Digital Converter with LVDS Outputs ...

Страница 2: ... 0 0 Figure 1 ADC12V170 Evaluation Board Connector and Jumper Locations Analog Input FIN 150 MHz Single Ended Clock Input 5 0V Power Connector ADC CLK_SEL DF Jumper PD Jumper Clock Buffer Reverse Side Analog Input Network Analog Input FIN 150 MHz FutureBus Connector ...

Страница 3: ...quencies greater than 150 MHz 2 ADC12V170LFEB low frequency version for input frequencies less than 150 MHz Please refer to the input circuit configurations described in the Analog Input Section 4 2 of this guide The location and description of the components on the ADC12V170 evaluation board can be found in Figure 1 as well as Section 5 0 Schematic and Section 7 0 Bill of Materials of this user s...

Страница 4: ...urther improve the noise performance of the ADC by filtering out the broadband noise of the clock source All results in the ADC12V170 datasheet are obtained with a tunable bandpass filter made by Trilithic Inc in the clock signal path The noise performance of the ADC12V170 can be improved further by making the edge transitions of the clock signal entering the ADC clock input pin 11 CLK very sharp ...

Страница 5: ...the ADC12V170 to provide the 1 5V common mode voltage required for the differential analog inputs VIN and VIN The ADC12V170 evaluation board is factory assembled with VRM connected to the transformer center tap through a 49 9Ω resistor to provide the necessary common mode voltage to the differential analog input 4 4 Board Outputs The digitized 12 bit output word from the ADC12V170 evaluation board...

Страница 6: ... the first half of the clock period and these lines will carry bit D10 during the second half of the clock period Similarly pins A10 B10 will carry D1 during the first half of the clock period and these pins will carry D0 during the second half of the clock period The DRDY signal which is used to capture the data is also in LVDS format and it is available at pins A4 D4 DRDY on the FutureBus connec...

Страница 7: ...ADC12V170 Evaluation Board User s Guide N 7 www national com Rev 0 0 5 0 Evaluation Board Schematic Figure 4 Signals ...

Страница 8: ...ADC12V170 Evaluation Board User s Guide N 8 www national com Rev 0 0 5 0 Schematic cont Figure 5 Power Distribution ...

Страница 9: ...ADC12V170 Evaluation Board User s Guide N 9 www national com Rev 0 0 6 0 Evaluation Board Layout Figure 6 Layer 1 Signal ...

Страница 10: ...ADC12V170 Evaluation Board User s Guide N 10 www national com Rev 0 0 6 0 Evaluation Board Layout cont Figure 7 Layer 2 Ground ...

Страница 11: ...ADC12V170 Evaluation Board User s Guide N 11 www national com Rev 0 0 6 0 Evaluation Board Layout cont Figure 8 Layer 3 Power ...

Страница 12: ...ADC12V170 Evaluation Board User s Guide N 12 www national com Rev 0 0 6 0 Evaluation Board Layout cont Figure 9 Layer 4 Signal ...

Страница 13: ...c_7343 Kemet 15 2 L1 L2 Ferrite Bead Core SMD FERRITE BEAD CORE 4 5X3 2X1 8 Panasonic ECG 16 1 JTAG Jumper 1x8 JUMPER BLOCK USING 8 PIN SIP HEADER Samtec 17 1 PD Jumper 2X2 2X2 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 18 1 CLK_SEL DF Jumper 2X4 2X4 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 19 1 Shunt PLACE SHUNT ACROSS PINS 7 8 ON CLK_SEL DF JUMPER FCI Electronic 20 1 U1...

Страница 14: ...ANTALUM 6 3V 10 sm c_7343 Kemet 15 2 L1 L2 Ferrite Bead Core SMD FERRITE BEAD CORE 4 5X3 2X1 8 Panasonic ECG 16 1 JTAG Jumper 1x8 JUMPER BLOCK USING 8 PIN SIP HEADER Samtec 17 1 PD Jumper 2X2 2X2 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 18 1 CLK_SEL DF Jumper 2X4 2X4 JUMPER BLOCK HEADER CUT TO SIZE FROM 2X6 HEADER Samtec 19 1 Shunt PLACE SHUNT ACROSS PINS 7 8 ON CLK_SEL DF JUMPER FCI...

Страница 15: ...tain life and whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the user 2 A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system or to affect its sa...

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