National Semiconductor ADC10080 Скачать руководство пользователя страница 4 | Manualshive

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National Semiconductor ADC10080 Скачать руководство пользователя страница 4

Pin No.

Symbol

Equivalent Circuit

Description

16–20, 23–

27

D0–D9

Digital output data. D0 is the LSB and D9 is the MSB of the binary
output word.

ANALOG POWER

2, 9, 10

V

DDA

Positive analog supply pins. These pins should be connected to a
quiet 3.0V source and bypassed to analog ground with a 0.1 µF
monolithic capacitor located within 1 cm of these pins. A 4.7 µF
capacitor should also be used in parallel.

3, 11, 14

V

SSA

Ground return for the analog supply.

DIGITAL POWER

22

V

DDIO

Positive digital supply pins for the ADC10080's output drivers. This
pin should be bypassed to digital ground with a 0.1 µF monolithic
capacitor located within 1 cm of this pin. A 4.7 µF capacitor should
also be used in parallel. The voltage on this pin should never
exceed the voltage on V

DDA

by more than 300 mV.

21

V

SSIO

The ground return for the digital supply for the output drivers. This
pin should be connected to the ground plane, but not near the
analog circuitry.

www.national.com

4

ADC10080

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Содержание ADC10080

Страница 1: ...rnal 1 2V preci sion bandgap reference is used to set the ADC full scale range and also allows the user to supply a buffered refer enced voltage for those applications requiring increased ac curacy The output data format is user choice of offset binary or two s complement This device is available in the 28 lead TSSOP package and will operate over the industrial temperature range of 40 C to 85 C Fe...

Страница 2: ...Ordering Information Industrial 40 C TA 85 C NS Package ADC10080CIMT 28 Pin TSSOP ADC10080CIMTX 28 Pin TSSOP Tape Reel ADC10080EVAL Evaluation Board Block Diagram 20048502 www national com 2 ADC10080 ...

Страница 3: ...pedance reference bypass pins only Connect a 0 1 µF capacitor from each of these pins to VSSA These pins should not be loaded VCOM may be used to set the input common input voltage VCM 8 VREFB DIGITAL I O 1 CLK Digital clock input The range of frequencies for this input is 20 MHz to 80 MHz The input is sampled on the rising edge of this input 15 DF DF 1 Two s Complement DF 0 Offset Binary 28 STBY ...

Страница 4: ...used in parallel 3 11 14 VSSA Ground return for the analog supply DIGITAL POWER 22 VDDIO Positive digital supply pins for the ADC10080 s output drivers This pin should be bypassed to digital ground with a 0 1 µF monolithic capacitor located within 1 cm of this pin A 4 7 µF capacitor should also be used in parallel The voltage on this pin should never exceed the voltage on VDDA by more than 300 mV ...

Страница 5: ...dface limits apply for TA TMIN to TMAX all other limits TA 25 C Notes 7 8 9 Symbol Parameter Conditions Min Typ Max Units STATIC CONVERTER CHARACTERISTICS No Missing Codes Guaranteed 10 Bits INL Integral Non Linearity Note 10 FIN 500 kHz 0 dB Full Scale 1 4 0 5 1 6 LSB DNL Differential Non Linearity FIN 500 kHz 0 dB Full Scale 0 9 0 25 1 0 LSB GE Gain Error Positive Error 1 6 0 5 2 0 FS Negative E...

Страница 6: ... 0 Output Voltage IOUT 1 6 mA 0 4 V DYNAMIC CONVERTER CHARACTERISTICS Note 11 ENOB Effective Number of Bits fIN 10 0 MHz 9 3 9 1 9 5 Bits fIN 39 MHz 9 3 8 9 9 5 Bits SNR Signal to Noise Ratio fIN 10 0 MHz 58 5 57 7 59 5 dB fIN 39 MHz 58 0 57 0 59 2 dB SINAD Signal to Noise Ratio Distortion fIN 10 0 MHz 58 0 56 3 59 2 dB fIN 39 MHz 57 6 55 6 59 0 dB 2nd HD 2nd Harmonic fIN 10 0 MHz 74 1 68 7 87 0 d...

Страница 7: ... C Note that the power dissipation of this device under normal operation will typically be about 78 6 mW The values for maximum power dissipation listed above will be reached only when the ADC10080 is operated in a severe fault condition Note 5 Human body model is 100 pF capacitor discharged through a 1 5 kΩ resistor Machine model is 220 pF discharged through 0Ω Note 6 The 235 C reflow temperature...

Страница 8: ...m a code of 01 1111 1111 to a code of 10 0000 0000 OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the output pins PIPELINE DELAY LATENCY is the number of clock cycles between initiation of conversion and when that data is pre sented to the output driver stage Data for any given sample is available at the output pins the Pipeline Delay plus ...

Страница 9: ...Timing Diagram 20048509 FIGURE 1 Clock and Data Timing Diagram Transfer Characteristics 20048510 FIGURE 2 Input vs Output Transfer Characteristic 9 www national com ADC10080 ...

Страница 10: ...tions apply VSSA VSSIO 0V VDDA 3 0V VDDIO 2 5V VIN 2 VP P STBY 0V VREF 1 2V External fCLK 80 MHz fIN 39 MHz 50 Duty Cycle DNL 20048512 DNL vs fCLK 20048515 DNL vs Clock Duty Cycle DC input 20048513 DNL vs Temperature 20048516 INL 20048514 INL vs fCLK 20048517 www national com 10 ADC10080 ...

Страница 11: ...INL vs Clock Duty Cycle 20048518 SNR vs VDDIO 20048519 SNR vs VDDA 20048520 SNR vs fCLK 20048521 INL vs Temperature 20048522 SNR vs Clock Duty Cycle 20048523 11 www national com ADC10080 ...

Страница 12: ...SNR vs Temperature 20048524 THD vs VDDA 20048525 THD vs VDDIO 20048526 THD vs fCLK 20048527 SNR vs IRS 20048528 THD vs IRS 20048529 www national com 12 ADC10080 ...

Страница 13: ...SINAD vs VDDA 20048530 SINAD vs VDDIO 20048531 THD vs Clock Duty Cycle 20048532 SINAD vs Clock Duty Cycle 20048533 THD vs Temperature 20048534 SINAD vs Temperature 20048535 13 www national com ADC10080 ...

Страница 14: ...SINAD vs fCLK 20048536 SFDR vs VDDIO 20048537 SINAD vs IRS 20048538 SFDR vs fCLK 20048539 SFDR vs VDDA 20048540 SFDR vs IRS 20048541 www national com 14 ADC10080 ...

Страница 15: ...DR vs Clock Duty Cycle 20048542 Spectral Response 10 MHz Input 20048543 SFDR vs Temperature 20048544 Spectral Response 39 MHz Input 20048545 Power Consumption vs fCLK 20048546 15 www national com ADC10080 ...

Страница 16: ...ing source tries to compensate for this it adds noise to the signal To prevent this use 18Ω series resistors at each of the signal input pins with a 25 pF capacitor across the inputs as shown in Figure 5 These components should be placed close to the ADC because the input pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input The two 18Ω resis...

Страница 17: ...beyond the specified 10 pF pin will cause tOD to increase making it difficult to prop erly latch the ADC output data The result could be an appar ent reduction in dynamic performance To minimize noise due to output switching minimize the load currents at the digital outputs This can be done by minimizing load capacitance and by connecting buffers between the ADC outputs and any other circuitry whi...

Страница 18: ...20048550 FIGURE 6 A Simple Application Using a Single Ended Driving Source www national com 18 ADC10080 ...

Страница 19: ...Physical Dimensions inches millimeters unless otherwise noted 28 Lead TSSOP Package Ordering Number ADC10080CIMT NS Package Number MTC28 19 www national com ADC10080 ...

Страница 20: ... THEIR PRODUCTS AND APPLICATIONS USING NATIONAL COMPONENTS PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE NATIONAL COMPONENTS BUYERS SHOULD PROVIDE ADEQUATE DESIGN TESTING AND OPERATING SAFEGUARDS EXCEPT AS PROVIDED IN NATIONAL S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS NATIONAL ASSUMES NO LIABILITY WHATSOEVER AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE S...

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