4
http://www.national.com
3.3.3 The Input Range Select (IRS) Pin
This pin has three states which the following table summarizes:
JP1 Jumper
setting
IRS State
Input Voltage
Range
(differential)
Pins 1&2
VDDA
2Vpp
Pins 3&4
VSSA
1.5Vpp
Open Floating 1.0Vpp
3.3.4 Power Supply Connections
Power to this board is supplied through power connector JS1. Table
1 describes the pin out, and the allowed voltage ranges
4.0 Obtaining Best Results
Many factors go into reasonable data capture when evaluating an
ADC. These include, but are not limited to, such things as PCB
layout, clock timing, the ratio between the input frequency and
sample rate and the FFT windowing technique.
Here we include very brief discussions on clock timing adjustments
as it relates to the ADC10080 and of sampling and FFT windowing.
4.1 Clock Timing
Because of differing delays in the clock signal and the data from the
ADC, at some sample rates the data from the ADC may be latched
as it is changing, leading to corrupted data, one example of which is
seen in
Figure 2
, which shows the poor data capture of a 4.7MHz
signal at 12.5Msps that results from poor timing of the clock and
external latch signals relative to each other.
Figure 2. Bad data capture of a 4.7MHz input signal at
12.5Msps due to attempted capture at data transition.
Figure 3 shows a successful data capture of a 4.7MHz input signal
at 12.5Msps with a shorting jumper on JS1.
Figure 3. A good data capture of a 4.7MHz input
signal at 12.5Msps
4.2 Coherent Sampling
Artifacts can result when we perform an FFT on a digitized
waveform, producing inconsistent results when performing repeated
testing. The presence of these artifacts means that the ADC under
test may perform better than the measurements would indicate.
We can eliminate the need for windowing and get more consistent
results if we observe the proper ratios between the input and
sampling frequencies. This greatly increases the spectral resolution
of the FFT, allowing us to more accurately evaluate the spectral
response of the A/D converter. When we do this, however, we must
be sure that the input signal has high spectral purity and stability
and that the sampling clock signal is extremely stable with minimal
jitter.
Coherent sampling of a periodic waveform occurs when a prime
integer number of cycles exists in the sample window. The
relationship between the number of cycles sampled (CY), the
number of samples taken (SS), the signal input frequency (fin) and
the sample rate (fs), for coherent sampling, is
CY
SS
f
in
f
s
=
CY, the number of cycles in the data record, must be a prime
integer number and SS, the number of samples in the data record,
must be a factor of 2 integer.
Further, fin (signal input frequency) and fs (sampling rate) should be
locked to each other. If these frequencies are locked to each other,
whatever frequency instability (jitter) is present in one of the signal
is present in the other signal and these jitter terms will cancel each
other.
Windowing (an FFT Option under WaveVision™) should be turned
off for coherent sampling. The results of coherent sampling can be
seen in the FFT plot seen in
Figure 4
. Note how narrow is the bin
(how fine are the lines) in this plot as compared with the plots of
Figures 5
through
7
.
Figure 4. Coherent sampling will indicate accurate
dynamic performance of the ADC
4.3 FFT Windowing Technique
Содержание ADC10040
Страница 7: ...7 http www national com ...
