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Connection and Functional Diagrams

(Continued)

Ordering Information

Part Number

Total

Package

Temperature

Unadjusted Error

Range

ADC0820BCV

V20A — Molded Chip Carrier

0˚C to +70˚C

ADC0820BCWM

⁄

LSB

M20B — Wide Body Small Outline

0˚C to +70˚C

ADC0820BCN

N20A — Molded DIP

0˚C to +70˚C

ADC0820CCJ

1 LSB

J20A — Cerdip

−40˚C to +85˚C

ADC0820CCWM

M20B — Wide Body Small Outline

0˚C to +70˚C

ADC0820CIWM

M20B — Wide Body Small Outline

−40˚C to +85˚C

ADC0820CCN

N20A — Molded DIP

0˚C to +70˚C

DS005501-2

FIGURE 1.

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Содержание ADC0820

Страница 1: ... 1 2 LSB and 1 LSB Features n Built in track and hold function n No missing codes n No external clocking n Single supply 5 VDC n Easy interface to all microprocessors or operates stand alone n Latched TRI STATE output n Logic inputs and outputs meet both MOS and T2 L voltage level specifications n Operates ratiometrically or with any reference value equal to or less than VCC n 0V to 5V analog inpu...

Страница 2: ...Chip Carrier 0 C to 70 C ADC0820BCWM 1 2 LSB M20B Wide Body Small Outline 0 C to 70 C ADC0820BCN N20A Molded DIP 0 C to 70 C ADC0820CCJ 1 LSB J20A Cerdip 40 C to 85 C ADC0820CCWM M20B Wide Body Small Outline 0 C to 70 C ADC0820CIWM M20B Wide Body Small Outline 40 C to 85 C ADC0820CCN N20A Molded DIP 0 C to 70 C DS005501 2 FIGURE 1 www national com 2 ...

Страница 3: ...haracteristics The following specifications apply for RD mode pin 7 0 VCC 5V VREF 5V and VREF GND unless otherwise speci fied Boldface limits apply from TMIN to TMAX all other limits TA Tj 25 C Parameter Conditions ADC0820BCN ADC0820CCN Limit Units ADC0820CCJ ADC0820BCV ADC0820BCWM ADC0820CCWM ADC0820CIWM Typ Tested Design Typ Tested Design Note 6 Limit Limit Note 6 Limit Limit Note 7 Note 8 Note ...

Страница 4: ...4 0 34 0 4 V Output Voltage DB0 DB7 OFL INT RDY IOUT TRI STATE VOUT 5V DB0 DB7 RDY 0 1 3 0 1 0 3 3 µA Output Current VOUT 0V DB0 DB7 RDY 0 1 3 0 1 0 3 3 µA ISOURCE Output VOUT 0V DB0 DB7 OFL 12 6 12 7 2 6 mA Source Current INT 9 4 0 9 5 3 4 0 mA ISINK Output Sink VOUT 5V DB0 DB7 OFL 14 7 14 8 4 7 mA Current INT RDY ICC Supply Current CS WR RD 0 7 5 15 7 5 13 15 mA AC Electrical Characteristics The...

Страница 5: ...2 3 4 5 500 ns to Next Conversion Note 4 See Graph Slew Rate Tracking 0 1 V µs CVIN Analog Input Capacitance 45 pF COUT Logic Output Capacitance 5 pF CIN Logic Input Capacitance 5 pF Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 A...

Страница 6: ...rcuits and Waveforms Timing Diagrams t1H DS005501 3 DS005501 4 tr 20 ns t0H DS005501 5 DS005501 6 tr 20 ns DS005501 7 Note On power up the state of INT can be high or low FIGURE 2 RD Mode Pin 7 is Low www national com 6 ...

Страница 7: ...rams Continued DS005501 8 FIGURE 3 WR RD Mode Pin 7 is High and tRD tI DS005501 9 FIGURE 4 WR RD Mode Pin 7 is High and tRD tI DS005501 10 FIGURE 5 WR RD Mode Pin 7 is High Stand Alone Operation www national com 7 ...

Страница 8: ...ure DS005501 35 Power Supply Current vs Temperature not including reference ladder DS005501 36 Accuracy vs tWR DS005501 37 Accuracy vs tRD DS005501 38 Accuracy vs tp DS005501 39 Accuracy vs VREF VREF VREF VREF DS005501 40 tI Internal Time Delay vs Temperature DS005501 41 Output Current vs Temperature DS005501 42 www national com 8 ...

Страница 9: ...z800 ns the preset internal time out tI after the rising edge of WR see Figure 4 or INT will go low after the falling edge of RD if RD goes low prior to the 800 ns time out see Figure 3 INT is reset by the rising edge of RD or CS see Figures 3 4 RD Mode INT going low indicates that the conversion is completed and the data result is in the output latch INT is reset by the rising edge of RD or CS se...

Страница 10: ...witches to the input Figure 8 the scheme can be expanded to make dual differential comparisons In this circuit the feedback switch and one input switch on each capacitor Z switches are closed in the zeroing cycle A comparison is then made by connecting the second input on each capacitor and open ing all of the other switches S switches The change in volt age at the inverter s input as a result of ...

Страница 11: ...ling edge of RD the MS flash converter goes from zero to compare mode and the LS ADC s comparators enter their zero cycle After 800 ns data from the MS flash is latched and the LS flash ADC enters compare mode Follow ing another 800 ns the lower 4 bits are recovered WR then RD Mode With the MODE pin tied high the A D will be set up for the WR RD mode Here a conversion is started with the WR in put...

Страница 12: ...must hold their charge Switch leakage and inverter bias current can cause errors if the comparator is left in this phase for too long Since the MS flash ADC enters its zeroing phase at the end of a conversion Section 1 3 a new conversion cannot be started until this phase is complete The minimum spec for this time tP Figures 2 3 4 5 is 500 ns DS005501 20 Note MS means most significant LS means lea...

Страница 13: ...Detailed Block Diagram DS005501 15 FIGURE 12 www national com 13 ...

Страница 14: ...the ADC0820 is shown in Fig ure 14 When a conversion starts WR low WR RD mode all input switches close connecting VIN to thirty one 1 pF ca pacitors Although the two 4 bit flash circuits are not both in their compare cycle at the same time VIN still sees all input capacitors at once This is because the MS flash converter is connected to the input during its compare interval and the LS flash is con...

Страница 15: ...ng already accomplish this function to a large degree Sec tion 1 2 Although the conversion time for the ADC0820 is 1 5 µs the time through which VIN must be 1 2 LSB stable is much smaller Since the MS flash ADC uses VIN as its com pare input and the LS ADC uses VIN as its zero input the ADC0820 only samples VIN when WR is low Sections 1 3 and 2 2 Even though the two flashes are not done simulta ne...

Страница 16: ...3 0 Typical Applications 8 Bit Resolution Configuration DS005501 26 9 Bit Resolution Configuration DS005501 27 www national com 16 ...

Страница 17: ...cations Continued Telecom A D Converter DS005501 28 VIN 3 kHz max 4VP No track and hold needed Low power consumption Multiple Input Channels DS005501 29 8 Bit 2 Quadrant Analog Multiplier DS005501 30 www national com 17 ...

Страница 18: ...3 0 Typical Applications Continued Fast Infinite Sample and Hold DS005501 31 www national com 18 ...

Страница 19: ...3 0 Typical Applications Continued Digital Waveform Recorder DS005501 32 www national com 19 ...

Страница 20: ...Physical Dimensions inches millimeters unless otherwise noted Hermetic Dual In Line Package J Order Number ADC0820CCJ NS Package Number J20A www national com 20 ...

Страница 21: ...ters unless otherwise noted Continued SO Package M Order Number ADC0820BCWM ADC0820CCWM or ADC0820CIWM NS Package Number M20B Molded Dual In Line Package N Order Number ADC0820BCN or ADC0820CCN NS Package Number N20A www national com 21 ...

Страница 22: ...e the failure of the life support device or system or to affect its safety or effectiveness National Semiconductor Corporation Americas Tel 1 800 272 9959 Fax 1 800 737 7018 Email support nsc com National Semiconductor Europe Fax 49 0 1 80 530 85 86 Email europe support nsc com Deutsch Tel 49 0 1 80 530 85 85 English Tel 49 0 1 80 532 78 32 Français Tel 49 0 1 80 532 93 58 Italiano Tel 49 0 1 80 5...

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