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Appendix A Specifications for VXI-MIO-64E-1



National Instruments Corporation

A-5

VXI-MIO Series User Manual

Analog Output

Output Characteristics

Number of channels .......................... 2 voltage

Resolution ......................................... 12 bits, 1 in 4,096

Max update rate

FIFO mode waveform generation

Internally timed ................... 1 MS/s per channel

All other cases ............................ 950 kS/s per channel

Type of DAC..................................... Double buffered, multiplying

FIFO buffer size ............................... 2,048 samples

Data transfers .................................... DMA, interrupts,

programmed I/O

Transfer Characteristics

Relative accuracy (INL)

After calibration..........................

0.3 LSB typ,

0.5 LSB max

Before calibration .......................

4 LSB max

DNL

After calibration..........................

0.3 LSB typ,

1.0 LSB max

Before calibration .......................

3 LSB max

Monotonicity ..................................... 12 bits, guaranteed after

calibration

Offset error

After calibration..........................

1.0 mV max

Before calibration .......................

200 mV max

Gain error (relative to internal reference)

After calibration..........................

0.01% of output max

Before calibration .......................

0.5% of output max

Содержание VXI-MIO Series

Страница 1: ...odules for VXIbus August 1996 Edition Part Number 321246A 01 Copyright 1996 National Instruments Corporation All Rights Reserved Click here to comment on this document via the National Instruments web...

Страница 2: ...6 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 905 785 0085 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 01 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645...

Страница 3: ...CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort includ...

Страница 4: ...1 1 What You Need to Get Started 1 2 Software Programming Choices 1 2 National Instruments Application Software 1 2 NI DAQ Driver Software 1 3 VXIplug play Instrument Drivers 1 4 Optional Equipment 1...

Страница 5: ...ignal Connections I O Connector 4 1 I O Connector Signal Descriptions 4 3 Analog Input Signal Connections 4 9 Types of Signal Sources 4 11 Floating Signal Sources 4 11 Ground Referenced Signal Sources...

Страница 6: ...SISOURCE Signal 4 34 Waveform Generation Timing Connections 4 34 WFTRIG Signal 4 36 UPDATE Signal 4 36 UISOURCE Signal 4 37 General Purpose Timing Signal Connections 4 38 GPCTR0_SOURCE Signal 4 38 GP...

Страница 7: ...Locator Diagram 2 4 Figure 2 3 VXI MIO 64XE 10 Logical Address Selection 2 5 Figure 2 4 SIMM Size Configuration 2 6 Figure 2 5 Load User Factory Configuration 2 8 Figure 2 6 Protect Change Factory Co...

Страница 8: ...4 15 TRIG1 Input Signal Timing 4 28 Figure 4 16 TRIG1 Output Signal Timing 4 28 Figure 4 17 TRIG2 Input Signal Timing 4 29 Figure 4 18 TRIG2 Output Signal Timing 4 29 Figure 4 19 STARTSCAN Input Signa...

Страница 9: ...s DRAM Configuration 2 6 Table 3 1 Available Input Configurations for the VXI MIO Series 3 3 Table 3 2 Actual Range and Measurement Precision 3 4 Table 3 3 Actual Range and Measurement Precision VXI M...

Страница 10: ...the VXI MIO Series modules lists what you need to get started describes the optional software and optional equipment and explains how to unpack your VXI MIO Series module Chapter 2 Configuration and I...

Страница 11: ...anual The indicates that the text following it applies only to specific VXI MIO Series modules Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a...

Страница 12: ...your system Use these manuals for hardware installation and configuration instructions specification information about your VXI DAQ hardware and application hints Software documentation You may have...

Страница 13: ...erations for Analog Signals Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products a...

Страница 14: ...ments DAQ STC system timing controller for timer related functions The DAQ STC consists of three timing groups that control analog input analog output and general purpose counter timer functions These...

Страница 15: ...ramming your National Instruments VXI DAQ hardware You can use LabVIEW LabWindows CVI Measure ComponentWorks VirtualBench or other application development environments with either NI DAQ or the VXIplu...

Страница 16: ...ame forms that can be used in popular spreadsheet programs and word processors VirtualBench features report generation and printing capabilities Using ComponentWorks LabVIEW LabWindows CVI or VirtualB...

Страница 17: ...an change platforms with minimal modifications to your code VXIplug play Instrument Drivers National Instruments distributes VXIplug play instrument drivers free of charge VXIplug play instrument driv...

Страница 18: ...onnector blocks SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3072 channels Low cha...

Страница 19: ...the analog and digital halves of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals Unpacking Your VXI MIO Series module is shipped in an antis...

Страница 20: ...range analog output reference source and other settings VXIbus Logical Address Each module in a VXIbus system is assigned a unique number between 0 and 254 This 8 bit number called the logical address...

Страница 21: ...cal address setting of either the VXI MIO Series module or the other module so that every module in the system has a different associated logical address To change the logical address of the VXI MIO S...

Страница 22: ...onal Instruments Corporation 2 3 VXI MIO Series User Manual Figure 2 1 VXI MIO 64E 1 Parts Locator Diagram 1 DRAM 2 Product Name 3 Assembly Number 4 P3 5 Serial Number 6 S1 7 S2 8 S3 9 Logical Address...

Страница 23: ...uments Corporation Figure 2 2 VXI MIO 64XE 10 Block Diagram Figure 2 3 shows the VXI MIO 64XE 10 switch settings for logical address 2 and 192 1 DRAM 2 Product Name 3 Assembly Number 4 P3 5 S1 6 S2 7...

Страница 24: ...t be of the same type Use bank 0 first when installing the SIMMs so that you can install up to 64 MB The VXI MIO module supports DRAM speeds of 80 ns or faster Use switch S3 to select the size of each...

Страница 25: ...gure 2 4 SIMM Size Configuration Refer to Table 2 1 to properly adjust the switch ON or OFF for all supported DRAM configurations Many of the DRAM options are available from National Instruments Table...

Страница 26: ...nfigured half instead of the user modified settings This is useful in the event that the user configured half of the EEPROM becomes corrupted in such a way that the VXI MIO module boots to an unusable...

Страница 27: ...6 for configuration settings Figure 2 6 Protect Change Factory Configuration Hardware Installation This section contains general installation instructions for the VXI MIO Series modules Consult your...

Страница 28: ...with the front panel of the mainframe 5 Tighten the retaining screws on the top and bottom edges of the front panel 6 Replace or close any doors or covers to the mainframe Software Installation Regar...

Страница 29: ...indows CVI release notes to install your application software After you have installed LabWindows CVI refer to the NI DAQ release notes and follow the instructions given there for your operating syste...

Страница 30: ...rporation 3 1 VXI MIO Series User Manual Hardware Overview Chapter 3 This chapter presents an overview of the hardware functions on your VXI MIO Series module Figure 3 1 shows the block diagram for th...

Страница 31: ...er Counter Timing I O RTSI Bus Interface DMA Interrupt Request Bus Interface ACH 48 63 ACH 32 47 ACH 16 31 ACH 0 15 Analog Input Control EEPROM Control EPF8282 DAQ STC Interface DMA Interface Bus Inte...

Страница 32: ...multimode scanning For example you can configure the circuitry to scan 48 channels 16 differentially configured channels and 32 single ended channels Table 3 1 describes the three input configurations...

Страница 33: ...o that you can configure each input channel uniquely The software programmable gain on this module increases its overall flexibility by matching the input signal ranges to those that the ADC can accom...

Страница 34: ...d The software programmable gain on this module increases its overall flexibility by matching the input signal ranges to those that the ADC can accommodate The VXI MIO 64XE 10 has gains of 1 2 5 10 20...

Страница 35: ...ertain the input signal will not be negative below 0 V unipolar input polarity is best However if the signal is negative or equal to zero using unipolar input polarity will yield inaccurate readings T...

Страница 36: ...measurement noise resulting in improved resolution For high speed applications not involving averaging or spectral analysis you may want to disable the dither to reduce noise You enable and disable th...

Страница 37: ...VXI MIO Series modules When scanning among channels at various gains the settling times may increase When the PGIA switches to a higher gain the signal on the previous channel may be well outside the...

Страница 38: ...4 V step It may take as long as 200 s for the circuitry to settle to this accuracy In general this extra settling time is not needed when the PGIA is switching to a lower gain Settling times can also...

Страница 39: ...nd 10 V You do not need to configure both channels for the same mode Analog Output Polarity Selection Selecting a bipolar range for a particular DAC means that any data written to that DAC will be int...

Страница 40: ...uency spectrum Notice that this reglitch circuit does not eliminate the glitches it only makes them more uniform in size Reglitching is normally disabled at startup and can be independently enabled fo...

Страница 41: ...this input via software Figure 3 3 Analog Trigger Block Diagram There are five analog triggering modes available as shown in Figures 3 4 through 3 8 You can set lowValue and highValue independently in...

Страница 42: ...enerated when the signal value is between the lowValue and the highValue Figure 3 6 Inside Region Analog Triggering Mode In high hysteresis analog triggering mode the trigger is generated when the sig...

Страница 43: ...ut section can be configured to acquire n scans after the analog input signal crosses a specific threshold As another example the analog output section can be configured to update its outputs whenever...

Страница 44: ...l circuitry These connections are designed to enable the VXI MIO Series module to both control and be controlled by other modules and circuits There are a total of 13 timing signals internal to the DA...

Страница 45: ...for different applications You can also individually enable each of the PFI pins to output a specific internal timing signal For example if you need the UPDATE signal as an output on the I O connector...

Страница 46: ...NI DAQ software the VXIbus trigger lines are functionally equivalent to RTSI bus trigger lines Figure 3 10 VXIbus Trigger Utilization Refer to the Timing Connections section of Chapter 4 for a descrip...

Страница 47: ...ix B Optional Cable Connector Descriptions for more information I O Connector Figure 4 1 shows the 96 pin I O connector pin assignments on the VXI MIO 64E 1 and VXI MIO 64XE 10 A signal description fo...

Страница 48: ...4 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 A ACH55 ACH61 ACH52 ACH58 ACH49 ACH47 ACH38 ACH44 ACH43 A...

Страница 49: ...ut Sense This pin serves as the reference node for any of channels ACH 16 63 in NRSE configuration DAC0OUT AOGND Output Analog Channel 0 Output This pin supplies the voltage output of analog output ch...

Страница 50: ...a low to high transition indicates the initiation of the pretrigger conversions PFI1 TRIG2 DGND Input Output PFI1 Trigger 2 As an input this is one of the PFIs As an output this is the TRIG2 signal In...

Страница 51: ...is the STARTSCAN signal This pin pulses once at the start of each analog input scan in the interval scan A low to high transition indicates the start of the scan PFI8 GPCTR0_SOURCE DGND Input Output P...

Страница 52: ...O 0 1 Short circuit to ground 5 at 10 V 5 at 10 V 20 V s DAC1OUT AO 0 1 Short circuit to ground 5 at 10 V 5 at 10 V 20 V s EXTREF AO 10 k 25 15 AOGND AO DGND DO 5 V DO 0 1 Short circuit to ground 1 A...

Страница 53: ...5 at 0 4 1 5 50 k pu GPCTR0_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu FREQ_OUT DO 3 5 at 4 6 V 5 at 0 4 1 5 50 k pu AI Analog Input DIO Digital Input Output pu pullup AO Analog Output DO Digital Outpu...

Страница 54: ...t circuit to ground 5 at 10 V 5 at 10 V 5 V s DAC1OUT AO 0 1 Short circuit to ground 5 at 10 V 5 at 10 V 5 V s AOGND AO DGND DO 5 V DO 0 1 Short circuit to ground 1A DIO 0 7 DIO 5 5 V 13 at 4 6 V 24 a...

Страница 55: ...module and your VXIbus system National Instruments is NOT liable for any damages resulting from such signal connections The maximum input voltage ratings are listed in Tables 4 1 and 4 2 in the Protec...

Страница 56: ...le depends on the configuration of the analog input channels you are using and the type of input signal source With the different configurations you can use the PGIA in different ways Figure 4 2 shows...

Страница 57: ...has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolated outputs and isolation amplifiers Tie...

Страница 58: ...ration Input Configurations You can configure your VXI MIO Series module for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measureme...

Страница 59: ...e Ended NRSE Floating Signal Source Not Connected to Earth Ground Grounded Signal Source Examples Ungrounded thermocouples Signal conditioning with isolated outputs Battery devices Examples Plug in in...

Страница 60: ...input each signal uses two multiplexer input lines one for the signal and one for its reference signal Therefore with a differential configuration for every channel up to 32 analog input channels are...

Страница 61: ...rential Input Connections for Ground Referenced Signals With this type of connection the PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal so...

Страница 62: ...not use the resistors and the source is truly floating the source is not likely to remain within the common mode signal range of the PGIA and the PGIA will saturate causing erroneous readings You mus...

Страница 63: ...connecting another resistor of the same value between the positive input and AIGND as shown in Figure 4 5 This fully balanced configuration offers slightly better noise rejection but has the disadvant...

Страница 64: ...t connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions You can software configure the VXI MIO Series module channels for two differ...

Страница 65: ...local ground reference is connected to the PGIA negative input The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the VXI MIO Series groun...

Страница 66: ...s to the module The PGIA can reject common mode signals as long as V in and V in are both within 11 V of AIGND Analog Output Signal Connections The analog output signals are DAC0OUT DAC1OUT EXTREF and...

Страница 67: ...ge 11 V peak with respect to AOGND Absolute maximum ratings 15 V peak with respect to AOGND AOGND is the ground reference signal for both analog output channels and the external reference signal Figur...

Страница 68: ...uts Warning Exceeding the maximum input voltage ratings which are listed in Tables 4 1 and 4 2 can damage the VXI MIO Series module National Instruments is NOT liable for any damages resulting from su...

Страница 69: ...your device National Instruments is NOT liable for damages resulting from such a connection Timing Connections Warning Exceeding the maximum input voltage ratings which are listed in Tables 4 1 and 4...

Страница 70: ...nections Programmable Function Input Connections There are a total of 13 internal timing signals that you can externally control from the PFI pins The source for each of these signals is software sele...

Страница 71: ...e detection mode In level detection mode there are no minimum or maximum pulse width requirements imposed by the PFIs themselves but limits may be imposed by the particular timing signal being control...

Страница 72: ...ultiplexers indicating when the input signal has been sampled and can be removed This signal has a 400 to 500 ns pulse width and is software enabled Figure 4 13 shows the timing for the SCANCLK signal...

Страница 73: ...ou can select any PFI pin as the source for TRIG1 and configure the polarity selection for either rising or falling edge The selected edge of the TRIG1 signal starts the data acquisition sequence for...

Страница 74: ...gnal Any PFI pin can externally input the TRIG2 signal which is available as an output on the PFI1 TRIG2 pin Refer to Figure 4 12 for the relationship of TRIG2 to the data acquisition sequence As an i...

Страница 75: ...ion will stop This mode acquires data both before and after receiving TRIG2 As an output the TRIG2 signal reflects the posttrigger in a pretriggered acquisition sequence This is true even if the acqui...

Страница 76: ...if you select internally triggered CONVERT As an output the STARTSCAN signal reflects the actual start pulse that initiates a scan This is true even if the starts are being externally triggered by an...

Страница 77: ...SCAN pulses by at least one scan period A counter on your VXI MIO Series module internally generates the STARTSCAN signal unless you select some external source This counter is started by the TRIG1 si...

Страница 78: ...CONVERT and configure the polarity selection for either rising or falling edge The selected edge of the CONVERT signal initiates an A D conversion As an output the CONVERT signal reflects the actual...

Страница 79: ...nless they occur within a data acquisition sequence Scans occurring within a data acquisition sequence may be gated by either the hardware AIGATE signal or software command register gate AIGATE Signal...

Страница 80: ...he SISOURCE signal in the level detection mode You can configure the polarity selection for the PFI pin for either active high or active low The maximum allowed frequency is 20 MHz with a minimum puls...

Страница 81: ...ter is started if you select internally generated UPDATE As an output the WFTRIG signal reflects the trigger that initiates waveform generation This is true even if the waveform generation is being ex...

Страница 82: ...y selection for either rising or falling edge The selected edge of the UPDATE signal updates the outputs of the DACs In order to use UPDATE you must set the DACs to posted update mode As an output the...

Страница 83: ...ted by the WFTRIG signal and can be stopped by software or the internal Buffer Counter D A conversions generated by either an internal or external UPDATE signal do not occur when gated by the software...

Страница 84: ...neral purpose timing signals are GPCTR0_SOURCE GPCTR0_GATE GPCTR0_OUT GPCTR0_UP_DOWN GPCTR1_SOURCE GPCTR1_GATE GPCTR1_OUT GPCTR1_UP_DOWN and FREQ_OUT GPCTR0_SOURCE Signal Any PFI pin can externally in...

Страница 85: ...e PFI9 GPCTR0_GATE pin As an input the GPCTR0_GATE signal is configured in the edge detection mode You can select any PFI pin as the source for GPCTR0_GATE and configure the polarity selection for eit...

Страница 86: ...r both options This signal is set to input High Z at startup Figure 4 31 shows the timing of the GPCTR0_OUT signal Figure 4 31 GPCTR0_OUT Signal Timing GPCTR0_UP_DOWN Signal This signal can be externa...

Страница 87: ...ource clock is being externally generated by another PFI This signal is set to input High Z at startup Figure 4 32 shows the timing requirements for the GPCTR1_SOURCE signal Figure 4 32 GPCTR1_SOURCE...

Страница 88: ...externally generated by another PFI This signal is set to input High Z at startup Figure 4 33 shows the timing requirements for the GPCTR1_GATE signal Figure 4 33 GPCTR1_GATE Signal Timing in Edge Det...

Страница 89: ...n functionality and leave the DIO7 pin free for general use Figure 4 35 shows the timing requirements for the GATE and SOURCE input signals and the timing specifications for the OUT output signals of...

Страница 90: ...e active edge of the source signal If an internal timebase clock is used the gate signal cannot be synchronized with the clock In this case gates applied close to a source edge take effect either on t...

Страница 91: ...traveling through areas with large magnetic fields or high electromagnetic interference Route signals to the module carefully Keep cabling away from noise sources A common noise source in many data ac...

Страница 92: ...t and least accurate whereas the last level is the slowest most difficult and most accurate Loading Calibration Constants Your VXI MIO Series module is factory calibrated before shipment at approximat...

Страница 93: ...tion the only significant residual calibration error could be gain error due to time or temperature drift of the onboard voltage reference External calibration addresses this error which is discussed...

Страница 94: ...e a 16 bit module the external reference should be at least 0 001 10 ppm accurate Other Considerations The CalDACs adjust the gain error of each analog output channel by adjusting the value of the ref...

Страница 95: ...of each module in the VXI MIO Series These specifications are typical at 25 C unless otherwise noted VXI MIO 64E 1 Analog Input Input Characteristics Number of channels 64 single ended or 32 different...

Страница 96: ...tion 25 V powered on 15 V powered off Inputs protected ACH 0 63 AISENSE AISENSE2 FIFO buffer size 8 192 S Data transfers DMA interrupts programmed I O Configuration memory size 512 words Input signal...

Страница 97: ...tion 2 5 mV max Postgain error after calibration 0 5 mV max Postgain error before calibration 100 mV max Gain error relative to calibration reference After calibration gain 1 0 02 of reading max Befor...

Страница 98: ...nt 20 ppm C Onboard calibration reference Level 5 000 V 0 5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Bandwidth Small signal 3 dB Large signal 1...

Страница 99: ...Double buffered multiplying FIFO buffer size 2 048 samples Data transfers DMA interrupts programmed I O Transfer Characteristics Relative accuracy INL After calibration 0 3 LSB typ 0 5 LSB max Before...

Страница 100: ...circuit to ground Power on state 0 V External reference input Range 11 V Overvoltage protection 25 V powered on 15 V powered off Input impedance 10 k Bandwidth 3 dB 1 MHz Dynamic Characteristics Sett...

Страница 101: ...y TTL CMOS Power on state Input High Z Data transfers Programmed I O Timing I O Number of channels 2 up down counter timers 1 frequency scaler Resolution Counter timers 24 bits Frequency scalers 4 bit...

Страница 102: ...er Source ACH 0 63 PFI0 TRIG1 Level full scale internal 10 V external Slope Positive or negative software selectable Resolution 8 bits 1 in 256 Hysteresis Programmable Bandwidth 3 dB 1 5 MHz internal...

Страница 103: ...ed by accessories 5 2 VDC 0 15 A typ 0 18 A max 2 VDC 0 04 A typ 0 06 A max 24 VDC 0 09 A typ 0 10 A max 24 VDC 0 09 A typ 0 10 A max Power available at I O connector 4 65 VDC to 5 25 VDC at 1 A Physi...

Страница 104: ...uaranteed Input coupling DC Maximum working voltage Each input should remain within 11 V of ground Overvoltage protection 25 V powered on 15 V powered off Inputs protected ACH 0 63 AISENSE AISENSE2 FI...

Страница 105: ...bration 76 V max Postgain error before calibration 102 mV max Gain error relative to calibration reference After calibration gain 1 30 5 ppm of reading max Before calibration 2 150 ppm of reading max...

Страница 106: ...8 LSB rms unipolar Gain 20 0 7 LSB rms bipolar 1 1 LSB rms unipolar Gain 50 1 1 LSB rms bipolar 2 0 LSB rms unipolar Gain 100 2 0 LSB rms bipolar 3 8 LSB rms unipolar Dynamic range 91 7 dB full scale...

Страница 107: ...ative accuracy INL 0 5 LSB typ 1 LSB max DNL 1 LSB max Monotonicity 16 bits guaranteed Offset error After calibration 305 V max Before calibration 20 mV max Gain error relative to internal reference A...

Страница 108: ...5 mV actual value stored in EEPROM Temperature coefficient 0 6 ppm C max Long term stability 6 ppm Digital I O Number of channels 8 input output Compatibility TTL CMOS Power on state Input High Z Data...

Страница 109: ...nter timers 20 MHz 100 kHz Frequency scaler 10 MHz 100 kHz Base clock accuracy 0 01 Max source frequency 20 MHz Min source pulse duration 10 ns edge detect mode Min gate pulse duration 10 ns edge dete...

Страница 110: ...Trigger Compatibility TTL Response Rising or falling edge Pulse width 10 ns min VXIbus Trigger Trigger lines Supports 5 TTL and 2 ECL trigger lines Power Requirement 5 VDC 2 82 A typ 3 38 A max Not i...

Страница 111: ...dix B This appendix describes the connectors on the optional cables for the VXI MIO Series modules Figure B 1 shows the pin assignments for the 68 pin MIO connector This connector is one of the two 68...

Страница 112: ...H6 ACH13 AIGND ACH4 AIGND ACH3 ACH10 AIGND ACH1 ACH8 DGND PFI8 GPCTR0_SOURCE PFI7 STARTSCAN GPCTR1_OUT PFI4 GPCTR1_GATE PFI3 GPCTR1_SOURCE PFI2 CONVERT DGND DGND DGND EXTSTROBE SCANCLK DIO3 DIO7 DIO2...

Страница 113: ...C NC NC NC NC NC NC NC ACH 55 ACH 54 ACH 61 ACH 52 ACH 51 ACH 58 ACH 49 ACH 48 ACH 47 ACH 38 ACH 37 ACH 44 AIGND ACH 35 ACH 34 ACH 41 ACH 32 ACH 23 ACH 30 ACH 21 ACH 20 ACH 27 ACH 18 ACH 17 ACH 24 NC...

Страница 114: ...nfigured independently with timing resolutions of 50 ns or 10 s With the DAQ STC you can interconnect a wide variety of internal timing signals to other internal blocks The interconnection scheme is q...

Страница 115: ...e VXI MIO 64E 1 or VXI MIO 64XE 10 modules 7 What is the best way to test my module without having to program the module The NI DAQ Configuration Utility formerly WDAQCONF has a Test menu with some ex...

Страница 116: ...voltage to another any DAC produces glitches due to released charges The largest glitches occur when the most significant bit MSB of the D A code switches You can build a lowpass deglitching filter t...

Страница 117: ...y when the analog output waveform generation starts If you are using NI DAQ call DAQ_Start with appropriate parameters If you are using LabVIEW invoke the AI Control VI with control code set to 0 star...

Страница 118: ...ers and counts how many points have been transferred If all the points have been transferred and the first instance of this error occurs NI DAQ returns a gpctrDataTransferWarning indicating that the e...

Страница 119: ...power on states of the PFI and DIO lines on the I O connector At system power on and reset both the PFI and DIO lines are set to high impedance by the hardware This means that the module circuitry is...

Страница 120: ...t through our technical support centers which are staffed by applications engineers Electronic Services National Instruments has BBS and FTP sites dedicated for 24 hour support with a collection of fi...

Страница 121: ...ional Instruments office in your country contact the source from which you purchased your software to obtain support Telephone Fax Australia 03 9879 5166 03 9879 6277 Austria 0662 45 79 90 0 0662 45 7...

Страница 122: ...__________________________________________________________ National Instruments hardware product model_________ Revision ________________________ Configuration ________________________________________...

Страница 123: ...____________________________________________________ Other Products Computer Model ______________________________________________________________ Microprocessor _______________________________________...

Страница 124: ...___________________________________________________________________________ _______________________________________________________________________________ ____________________________________________...

Страница 125: ...es User Manual Symbols degree negative of or minus ohm per percent plus or minus positive of or plus square root of 5V 5 VDC source signal Prefix Meaning Value p pico 10 12 n nano 10 9 micro 10 6 m mi...

Страница 126: ...nel signal A D analog to digital ADC A D converter address space A set of 2n memory locations differentiated from other such sets in VXI VMEbus systems by six addressing lines known as address modifie...

Страница 127: ...itive and negative values for example 5 to 5 V bit One binary digit either 0 or 1 bus The group of conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehi...

Страница 128: ...cturer address space and memory requirements In order to support automatic system and memory configuration the VXIbus specification requires that all VXIbus devices have a set of such registers 2 The...

Страница 129: ...XIbus system as a single device Some examples of devices are computers multimeters multiplexers oscillators operator interfaces and counters DGND digital ground signal DIFF differential mode different...

Страница 130: ...o of the largest signal level a circuit can handle to the smallest signal level it can handle usually taken to be the noise level normally expressed in dB E ECL Emitter Coupled Logic EEPROM electrical...

Страница 131: ...time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device floating signal sources Signal sources with voltage signals that are not connecte...

Страница 132: ...nts of a computer system such as the circuit boards plug in boards chassis enclosures peripherals cables and so on hardware triggering A form of triggering where you set the start time of an acquisiti...

Страница 133: ...where there is a longer interval between scans than there is between individual channels comprising a scan I O input output The transfer of data to from a computer system involving communications cha...

Страница 134: ...ard assembly and its associated mechanical parts front panel optional shields and so on A module contains everything required to occupy one or more slots in a mainframe MSB most significant bit multit...

Страница 135: ...oftware OLE also makes it possible to create compound documents consisting of multiple sources of information from different applications onboard channels Channels provided by the plug in data acquisi...

Страница 136: ...such as the earth or a building ground Also called grounded signal sources relative accuracy A measure in LSB of the accuracy of an ADC It includes all non linearity and quantization errors It does n...

Страница 137: ...se from the scan clock produces one scan which acquires one new sample from every analog input channel in the group scan clock The clock controlling the time interval between scans On boards with inte...

Страница 138: ...through software that is it is not dynamically configurable system A system consists of one or more mainframes that are connected all sharing a common Resource Manager Each device in a system has a u...

Страница 139: ...to every analog output channel in the group UPDATE update signal update rate The number of output updates per second V V volts VDC volts direct current VI Virtual Instrument 1 A combination of hardwa...

Страница 140: ...ts VXIplug play Systems A group of VXI developers dedicated to making VXI devices as Alliance easy to use as possible primarily by simplifying software development W waveform Multiple voltage readings...

Страница 141: ...amplifier characteristics VXI MIO 64E 1 A 3 VXI MIO 64XE 10 A 11 analog input 3 3 to 3 9 common questions about C 2 to C 4 considerations for selecting input ranges 3 6 dither 3 7 to 3 8 input modes...

Страница 142: ...board configuration See configuration bulletin board support D 1 C cables See also I O connectors field wiring considerations 4 45 optional cable connectors 68 pin extended analog input connector pin...

Страница 143: ...4 15 illustration 4 15 nonreferenced or floating signal sources 4 16 to 4 17 illustration 4 16 recommended configuration figure 4 13 single ended connections 4 18 floating signal sources RSE 4 19 grou...

Страница 144: ...orm generation timing connections 4 44 frequently asked questions See questions about VXI MIO series FTP support D 1 G general purpose timing signal connections 4 38 to 4 44 FREQ_OUT signal 4 44 GPCTR...

Страница 145: ...to 4 20 available input modes 3 3 to 3 4 DIFF table 3 3 NRSE table 3 3 RSE table 3 3 common mode signal rejection 4 20 differential connections DIFF input configuration 4 14 floating signal sources 4...

Страница 146: ...VERT signal description table 4 4 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 PFI3 GPCTR1_SOURCE signal description table 4 4 VXI MIO 64E 1 table 4 6 VXI MIO 64XE 10 table 4 8 PFI4 GPCTR1_GATE s...

Страница 147: ...1 to C 2 installation and configuration C 2 timing and digital I O C 4 to C 6 R reference selection analog output 3 10 referenced single ended input RSE See RSE referenced single ended input reglitch...

Страница 148: ...4 programmable function input connections 4 24 to 4 25 waveform generation timing connections 4 34 to 4 38 UISOURCE signal 4 37 to 4 38 UPDATE signal 4 36 to 4 37 WFTRIG signal 4 34 types of signal so...

Страница 149: ...A 7 VXI MIO 64XE 10 A 14 STARTSCAN signal timing connections 4 30 to 4 31 input timing figure 4 30 output timing figure 4 31 T technical support D 1 to D 2 theory of operation See hardware overview ti...

Страница 150: ...gure 3 13 below low level triggering mode figure 3 12 block diagram 3 12 high hysteresis triggering mode 3 13 inside region triggering mode figure 3 13 low hysteresis triggering mode 3 14 specificatio...

Страница 151: ...ng choices ComponentWorks 1 2 LabVIEW and LabWindows CVI 1 3 NI DAQ driver software 1 3 to 1 4 VirtualBench 1 3 unpacking 1 6 VXIplug play instrument drivers 1 4 to 1 5 VXIplug play instrument drivers...

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