Chapter 2
NI SPEEDY-33 Functional Description and Interface
©
National Instruments Corporation
2-3
Figure 2-2 shows the architectural details of the VC33 DSP.
Figure 2-2.
VC33 DSP Functional Block Diagram
C
a
che
(64 x
3
2)
C
a
che
(64 x
3
2)
C
a
che
(64 x
3
2)
RAM
Block 0
(1 k x
3
2)
C
a
che
(64 x
3
2)
C
a
che
(64 x
3
2)
Boot
Lo
a
der
C
a
che
(64 x
3
2)
C
a
che
(64 x
3
2)
RAM
Block 1
(1 k x
3
2)
RAM
Block 2
(16 k x
3
2)
RAM
Block
3
(16 k x
3
2)
3
2
3
2
3
2
24
24
3
2
24
24
24
24
3
2
24
3
2
24
3
2
24
3
2
24
3
2
PDATA B
us
PADDR B
us
DDATA B
us
DADDR1 B
us
DADDR2 B
us
DMADATA B
us
DMAADDR B
us
MUX
PAGE0
PAGE1
PAGE2
PAGE
3
RDT
HOLD
HOLDA
S
TRB
RW
D
3
1-D0
A2
3
-A0
R
S
W0,1
S
HZ
EDGEMODE
RE
S
ET
INT(
3
–0)
IACK
MCBL/NP
XF(1,0)
TDI
TDO
EMU0
ENU1
TCK
TM
S
TR
S
T
EXTCLK
XOUT
XIH
H1
H
3
CLKND(0,1)
MUX
IR
PC
Controller
JT
A
G
Em
u
l
a
tion
PLL CLK
CPU1
CPU1
MUX
3
2
3
2
3
2
40
40
40
40
40
40
40
M
u
ltiplier
3
2-Bit
B
a
rrel
S
hifter
ALU
Extended-
Preci
s
ion
Regi
s
ter
(R7-R0)
40
3
2
DI
S
P0, IR0, IR1
ARAU1
BK
ARAU0
24
24
3
2
3
2
3
2
24
24
3
2
3
2
3
2
A
u
xili
a
ry
Regi
s
ter
s
(AR0-AR7)
Other
Regi
s
ter
s
(12)
DMA Controller
Glo
ba
l-Control
Regi
s
ter
S
eri
a
l-Port-Control
Regi
s
ter
S
o
u
rce-Addre
ss
Regi
s
ter
De
s
tin
a
tion-
Addre
ss
Regi
s
ter
Tr
a
n
s
fer-Co
u
nter
Regi
s
ter
Receive/Tr
a
n
s
mit
(R/X) Timer Regi
s
ter
D
a
t
a
-Tr
a
n
s
mit
Regi
s
ter
D
a
t
a
-Receive
Regi
s
ter
S
eri
a
l Port 0
Peripher
a
l D
a
t
a
B
us
Glo
ba
l-Control
Regi
s
ter
Timer-Period
Regi
s
ter
Timer-Co
u
nter
Regi
s
ter
Timer 0
Glo
ba
l-Control
Regi
s
ter
Timer-Period
Regi
s
ter
Timer-Co
u
nter
Regi
s
ter
Timer 1
S
TRB-Control
Regi
s
ter
Port Control
F
S
X0
DX0
CLKX0
F
S
R0
DR0
CLKR0
TCLK1
TCLK0
CPU2
REG1
REG2
Pe
ri
p
h
e
r
a
l Addre
ss
B
us
P
e
ri
pher
a
l D
a
t
a
B
us
REG1
