Caution
If the Access LED is observed to be solid red, a hardware failure has been
detected that may impact the performance of the PXIe-6674. Contact National
Instruments for support.
Active LED
You can set the Active LED to amber.
Tip
Changing the Active LED color to amber is helpful when you want to identify
devices in a multichassis situation, or when you want an indication that your
application has reached a predetermined section of the code.
Hardware Features
The PXIe-6674 performs two broad functions.
•
Generating clock and trigger signals.
•
Routing internally or externally generated signals from one location to another.
on page 10 outlines the function and direction of the signals discussed in detail in the
remainder of this chapter.
Table 3. Signal Descriptions
Signal Name
Direction
Description
PXI_CLK10
In (from
chassis)
This signal is the PXI 10 MHz backplane clock. This
signal is the output of the native 100 MHz oscillator in the
chassis divided by ten.
PXIe_CLK100
In (from
chassis)
This signal is the PXI Express 100 MHz backplane clock.
PXIe-CLK100 offers tighter slot to slot timing than
PXI_CLK10.
CLKIN
In (from
front panel)
CLKIN is the signal connected to the SMA input
connector of the same name. CLKIN is connected to the
FPGA for use as a synchronization clock.
CLKOUT
Out (to front
panel)
CLKOUT is the signal on the SMA output connector of
the same name. CLKOUT can be sourced from the
OCXO, PXI_CLK10, Clock Generation, or from the
PXIe_DSTARA network.
Clock Generation Out
(internal)
Clock Generation refers to the clock signal coming from
the onboard clock generation circuitry of the PXIe-6674.
The clock generation circuitry can generate a clock from
sub-1 Hz to 1 GHz with fine granularity and is
automatically locked in phase to PXIe_CLK100.
10
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PXIe-6674 User Manual
