background image

Table 4. Resolution by Frequency Ranges

Clock Generation Frequency

Resolution

 

 

18.75 MHz to 37.5 MHz

0.355 ΩHz

37.5 MHz to 75 MHz

0.711 ΩHz

75 MHz to 150 MHz

1.42 ΩHz

150 MHz to 300 MHz

2.84 ΩHz

300 MHz to 600 MHz

5.68 ΩHz

600 MHz to 1 GHz

11.4 ΩHz

ClkIn

CLKIN can be routed to the FPGA and used as a trigger synchronization clock inside the
FPGA.

Because the PXIe-6674 is not designed for use in the system timing slot, it can not drive
CLKIN to PXI_CLK10_IN for overdriving PXI_CLK10 and PXIe_CLK100. The PXIe-6674T
is required for this functionality.

PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC

The PXI Express architecture includes a set of three high speed differential signal paths to
connect the system timing slot to each PXI Express peripheral slot (up to 17 peripheral slots).
These signals are PXIe_DSTARA, PXIe_DSTARB, and PXIe_DSTARC.

PXIe_DSTARA—PXIe_DSTARA is used to send clock signals from the system timing
slot to each PXI Express peripheral slot in a star configuration. PXIe_DSTARA uses
LVPECL signaling and closely matched trace lengths to achieve low skew, high speed
clock routing capabilities. The PXIe-6674 can route its DSTARA to CLKOUT and
PFI_LVDS.

PXIe_DSTARB—PXIe_DSTARB is used to send trigger signals from the system timing
slot to each PXI Express peripheral slot in a star configuration. PXIe_DSTARB uses
LVDS signaling and closely matched trace lengths to achieve faster, more precise
triggering than is achievable with PXI_STAR or PXI_TRIG.

PXIe_DSTARC—PXIe_DSTARC is used to send trigger signals from each PXI Express
peripheral slot to the system timing slot in a star configuration. PXIe_DSTARC uses
LVDS signaling and closely matched trace lengths and can be used to send a trigger
signal or clock signal to the system timing module.

PFI_LVDS<0..2>

To allow for sending and receiving signals between system timing modules that are too fast for
single ended PFI signaling, two PFI SMA connectors can be combined to send or receive
LVDS signals. 

Table 5.

 on page 14 shows the relation between the front panel SMA

connectors used for PFI and PFI_LVDS.

PXIe-6674 User Manual

  | 

© National Instruments

  | 

13

Содержание PXIe-6674

Страница 1: ...tware Use the documentation you have as follows Measurement hardware documentation This documentation contains detailed information about the measurement hardware that plugs into or is connected to the computer Use this documentation for hardware installation and configuration instructions specifications about the measurement hardware and application hints Software documentation Refer to the NI Sy...

Страница 2: ...you to share clocks and triggers between modules in a PXI Express chassis and other PXI chassis or non PXI systems This is done without using the system timing slot in your PXI Express chassis The PXIe 6674 module generates and routes clock signals between devices in multiples chassis providing a method for synchronizing multiple devices in a PXI Express system What You Need to Get Started To set ...

Страница 3: ...EW Data Acquisition VI Library a series of virtual instruments for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW LabWindows CVI is a complete ANSI C ADE that features an interactive user interface code generation tools and the LabWindows CVI Data Acquisition and Easy I O libraries Safety Information The following section contains important safety information that yo...

Страница 4: ...stand voltage levels that commonly occur in electrical distribution systems The following is a description of measurement categories Measurement Category I is for measurements performed on circuits not directly connected to the electrical distribution system referred to as MAINS voltage This category is for measurements of voltages from specially protected secondary circuits Such voltage measureme...

Страница 5: ...press chassis The PXIe 6674 can be placed in any PXI Express slot as indicated by the glyph in Figure 1 on page 5 Figure 1 PXI Express Slot Indicator Glyph 3 Remove the filler panel for the selected slot if applicable 4 Ground yourself using a grounding strap or by touching a grounded object Follow the ESD protection precautions described in the Unpacking section of the Introduction 5 Carefully in...

Страница 6: ... on the front panel provide information about module status The front panel descriptions in the Hardware Overview describe the LEDs in greater detail Hardware Overview This chapter presents an overview of the hardware functions of the PXIe 6674 Figure 2 on page 7 provides a functional overview of the PXIe 6674 hardware 6 ni com PXIe 6674 User Manual ...

Страница 7: ...LK100 PXIe_DSTARB Peripheral PXIe_DSTARC Peripheral PFI 0 Threshold DAC PFI 0 Driver Comparator Driver Comparator PFI 1 Threshold DAC LVDS Driver Receiver PFI 1 PFI 2 Threshold DAC PFI 2 Driver Comparator Driver Comparator PFI 3 Threshold DAC LVDS Driver Receiver PFI 3 PFI 4 Threshold DAC PFI 4 Driver Comparator Driver Comparator PFI 5 Threshold DAC LVDS Driver Receiver PFI 5 PFI_LVDS 0 2 PFI 0 5 ...

Страница 8: ...el 1 2 3 5 4 Timing Module NI PXIe 6674 PFI 0 LVDS 0 PFI 1 LVDS 0 PFI 2 LVDS 1 PFI 3 LVDS 1 PFI 5 LVDS 2 PFI 4 LVDS 2 CLK OUT CLK IN 1 Access LED 2 Active LED 3 CLKOUT Connector 4 PFI 0 5 PFI_LVDS 0 2 Connectors 5 CLKIN Connector 8 ni com PXIe 6674 User Manual ...

Страница 9: ...has initiated the module Amber Module is being accessed The Access LED flashes amber for 50 ms when the module is accessed Blinking Red Module has detected an over temperature condition Solid Red A hardware error has been detected Caution If the Access LED is observed to be blinking red the module has detected an over temperature condition Continued use of the PXIe 6674 in this condition is not re...

Страница 10: ...n Description PXI_CLK10 In from chassis This signal is the PXI 10 MHz backplane clock This signal is the output of the native 100 MHz oscillator in the chassis divided by ten PXIe_CLK100 In from chassis This signal is the PXI Express 100 MHz backplane clock PXIe CLK100 offers tighter slot to slot timing than PXI_CLK10 CLKIN In from front panel CLKIN is the signal connected to the SMA input connect...

Страница 11: ...GA PXI_TRIG 0 7 In Out to from chassis The PXI trigger bus consists of eight digital lines shared among all slots in the PXI Express chassis The PXIe 6674 can route a wide variety of signals to and from these lines Note PXI_TRIG 0 5 are also known as RTSI 0 5 in some hardware devices and APIs However PXI_TRIG 6 7 are not identical to RTSI 6 7 PXI_STAR In Out to from chassis The PXI star trigger bu...

Страница 12: ...4 for routing clock signals Clock Generation The PXIe 6674 includes built in advanced clock generation circuitry for generating clock signals below 1 Hz to 1 GHz with very fine frequency resolution The clock generation circuitry is based on a direct digital synthesis DDS with an 800 MHz reference phase locked to PXIe_CLK100 This allows the DDS to generate a 150 MHz to 300 MHz signal with microhert...

Страница 13: ...n a star configuration PXIe_DSTARA uses LVPECL signaling and closely matched trace lengths to achieve low skew high speed clock routing capabilities The PXIe 6674 can route its DSTARA to CLKOUT and PFI_LVDS PXIe_DSTARB PXIe_DSTARB is used to send trigger signals from the system timing slot to each PXI Express peripheral slot in a star configuration PXIe_DSTARB uses LVDS signaling and closely match...

Страница 14: ... LVDS Triggers section for details on using PFI_LVDS for sending and receiving trigger signals CLKOUT The CLKOUT SMA connector on the front panel provides a means to export a clock signal from the PXIe 6674 to an external device or another system timing module The CLKOUT driver uses two separate circuits for driving CLKOUT one for low speed frequencies 50 MHz and below and one for high speed above...

Страница 15: ...RCE 3 PXI_STAR 0 16 PXI_TRIG 0 7 PFI 0 5 PFI_LVDS 0 2 PXIe_DSTARC 0 16 Steady Logic and Software Trigger are routed to SOURCE of each Selection Circuitry block SYNCHRONIZATION CLOCKS for PXI_STAR 0 16 PXI_TRIG 0 7 and PXIe DSTARB 0 16 Selection Circuitry Selection Circuitry Selection Circuitry PFI 0 PFI 1 PFI 2 PFI 3 PFI 4 PFI 5 PFI_LVDS 0 PFI_LVDS 1 PFI_LVDS 2 Selection Circuitry PXIe_DSTARB 0 PX...

Страница 16: ...ignal routing operations can be characterized by a source input and a destination In addition synchronous routing operations must also define a third signal known as the synchronization clock Refer to the Choosing the Type of Routing section for more information on synchronous routing versus asynchronous routing Figure 6 on page 17 summarizes the sources and destinations of the PXIe 6674 16 ni com...

Страница 17: ...nce and minimize reflections Note Terminating the signals with a 50 Ω resistance is recommended when the source is another PXIe 6674 or any other source with a 50 Ω output The voltage thresholds for the front panel PFI inputs are programmable The input signal is generated by comparing the input voltage on the PFI connectors to the voltage output of software programmable DACs The thresholds for the...

Страница 18: ...s You can independently select the output signal source for each of the PFI lines from one of the following sources Another PFI 0 5 Another PFI pair in LVDS mode PXI_TRIG 0 7 PXI_STAR Global software trigger PFI synchronization clock PXIe_DSTARB Steady logic high or low The PFI synchronization clock may be any of the following signals Clock Generation PXI_CLK10 PXIe_CLK100 CLKIN Any of the previou...

Страница 19: ...XI_CLK10 PXIe_CLK100 CLKIN Any of the previously listed signals divided by the first frequency divider 2n up to 512 Any of the previously listed signals divided by the second frequency divider 2m up to 512 Refer to the Choosing the Type of Routing section for more information on the synchronization clock Note The PFI synchronization clock is the same for all routing operations in which PFI 0 5 or ...

Страница 20: ... Type of Routing section for more information about the synchronization clock Note The backplane synchronization clock is the same for all routing operations in which PXI_TRIG 0 7 PXIe_DSTARC or PXI_STAR is defined as the output although the divide down ratio for this clock full rate first divider second divider may be chosen on a per route basis Using the PXI Star Trigger There are up to 17 PXI s...

Страница 21: ...eripheral modules using PXIe_DSTARB Both PXIe_DSTARB and PXIe_DSTARC are one directional The PXI Express Specification requires PXI Express chassis to limit the skew between any two PXIe_DSTAR routes to 150 ps The PXIe 6674 receives PXIe_DSTARB and can route it as a trigger source The PXIe 6674 can independently select from the following sources to be routed to PXIe_DSTARC PFI 0 5 PFI_LVDS 0 2 PXI...

Страница 22: ... source Propagation delay of the signal across the backplane s and cable s Propagation delay of the signal through the PXIe 6674 Time for the receiver to recognize the signal Both the source and the destination of an asynchronous routing operation on the PXIe 6674 can be any of the following lines Any front panel PFI pin PFI 0 5 as single ended Any front panel PFI pin as LVDS PFI_LVDS 0 2 Any PXI ...

Страница 23: ...owever if the trigger is sent and received synchronously using a low skew synchronization clock for example PXI_CLK10 all receiving devices can act on the trigger at the same time as shown in Figure 9 on page 23 Figure 9 Synchronous Routing to Multiple Destinations PXI_CLK10 Trigger Destination 2 Trigger Destination 1 Trigger Out Source Trigger Synchronously Received Destinations 1 and 2 A B A Pro...

Страница 24: ...tions simultaneously you must ensure that the input is table within the setup and hold window around the synchronization clock edge For more information and possible methods to ensure this requirement is met go to ni com info and enter the Info Code SyncTriggerRouting Possible sources for synchronous routing with the PXIe 6674 include the following sources Any front panel PFI pin as single ended A...

Страница 25: ...ncy The OCXO frequency can be varied over a small range The output frequency of the OCXO is adjusted using this constant to meet the specification listed in the PXIe 6674 Specifications PXI_CLK10 Phase When using the PLL to lock PXI_CLK10 to an external reference clock the phase between the clocks can be adjusted The time between rising edges of PXI_CLK10 and the input clock is minimized using thi...

Страница 26: ...tic environment Operation of this hardware in a residential area is likely to cause harmful interference Users are required to correct the interference at their own expense or cease operation of the hardware Changes or modifications not expressly approved by National Instruments could void the user s right to operate the hardware under the local regulatory rules Caution To ensure the specified EMC...

Страница 27: ... Warranty This Limited Warranty does not apply if the defect of the product resulted from improper or inadequate maintenance installation repair or calibration performed by a party other than NI unauthorized modification improper environment use of an improper hardware or software key improper use or operation outside of the specification for the product improper voltages accident abuse or neglect...

Страница 28: ...National Instruments _Legal Information txt for information on including legal information in installers built with NI products U S Government Restricted Rights If you are an agency department or other entity of the United States Government Government the use duplication reproduction release modification disclosure or transfer of the technical data included in this manual is governed by the Restri...

Страница 29: ...and xPC TargetBox are registered trademarks and Simulink Coder TargetBox and Target Language Compiler are trademarks of The MathWorks Inc Tektronix Tek and Tektronix Enabling Technology are registered trademarks of Tektronix Inc The Bluetooth word mark is a registered trademark owned by the Bluetooth SIG Inc The ExpressCard word mark and logos are owned by PCMCIA and any use of such marks by Natio...

Страница 30: ...ND SHUT DOWN MECHANISMS NI EXPRESSLY DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY OF FITNESS OF THE PRODUCTS OR SERVICES FOR HIGH RISK USES Information is subject to change without notice Refer to the NI Trademarks and Logo Guidelines at ni com trademarks for information on NI trademarks Other product and company names mentioned herein are trademarks or trade names of their respective companies For p...

Отзывы: