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3-3
Trigger Filters
You can enable a programmable debouncing filter on each PXI_Trig, PXIe_DSTAR, or
PXI_STAR signal. When the filters are enabled, your module samples the input on each rising
edge of a filter clock. This filter clock is generated using the onboard oscillator.
The following example explains how the filter works for low-to-high transitions of the input
signal. High-to-low transitions work similarly.
Assume that an input terminal has been low for a long time. The input terminal then changes
from low to high, but glitches several times. When the filter clock has sampled the signal high
on N consecutive edges, the low-to-high transition is propagated to the rest of the circuit. The
value of N depends on the filter setting. Refer to Table 3-2.
The filter setting for each input can be configured independently. At power on, the filters are
disabled.
Enabling filters introduces jitter on the input signal. The maximum jitter is one period of the
timebase.
These filters work by rejecting any pulse shorter than the specified filter setting. For example, a
5.12
μ
s filter will reject any pulses shorter than 5.12
μ
s. The trigger filters can be used to prevent
false triggers from occurring in cases where the trigger signal is noisy or glitchy.
Table 3-2.
Trigger Debouncing Filters
Filter
Setting
Filter Clock
N (Filter Clocks
Needed to Pass
Signal)
Pulse Width
Guaranteed to
Pass Filter
Pulse Width
Guaranteed to
Not Pass Filter
None
—
—
—
—
90 ns
(short)
100 MHz
9
90 ns
80 ns
5.12
μ
s
(medium)
100 MHz
512
5.12
μ
s
5.11
μ
s
2.56 ms
(high)
100 kHz
256
2.56 ms
2.55 ms
Custom
User
Configurable
N
N/timebase
(N – 2)/timebase